Abstract: The display substrate includes a base substrate and a plurality of pixel units disposed on the base substrate. Each of the pixel units is composed of 5 sub-pixels. The 5 sub-pixels include 1 red sub-pixel, 2 green sub-pixels, 1 blue sub-pixel and 1 white sub-pixel. Each of the sub-pixels includes a white light emitting unit. The red sub-pixel, the green sub-pixels and the blue sub-pixel further include color film layers corresponding to respective light emitting colors of the red sub-pixel, the green sub-pixels and the blue sub-pixel. The white sub-pixel is adjacent to the blue sub-pixel, and an aperture area of the blue sub-pixel is smaller than that of the green sub-pixels and smaller than that of the red sub-pixel.

Abstract: The present disclosure provides a display panel, a method of manufacturing the same, and a display device. The initialization signal line layer in the display panel includes an initialization signal line pattern arranged in each of the plurality of sub-pixel areas; the first auxiliary signal line layer includes a plurality of first auxiliary signal line patterns corresponding to the plurality of sub-pixel areas in a one-to-one manner, and the first auxiliary signal line pattern is coupled to an initialization signal line pattern in a corresponding sub-pixel area, at least part of the first auxiliary signal line pattern extends along the first direction, and first auxiliary signal line patterns corresponding to sub-pixel areas in a same row of sub-pixel areas are sequentially coupled.

Abstract: Some embodiments of the disclosure provide an air intake bypass recirculation structure with adjustable air entraining amount and controllable broadband noise which includes main body of the air intake bypass recirculation structure and an air entraining amount adjusting structure. In some examples, an air intake bypass recirculation cavity is formed in the main body of the air intake bypass recirculation structure. An air inlet of an air intake pipe and an air outlet of the air intake pipe are formed in two ends of the main body of the air intake bypass recirculation structure respectively. An airflow inlet of the air intake bypass recirculation structure and an airflow outlet of the air intake bypass recirculation structure are formed in the inner side of the main body of the air intake bypass recirculation structure. The air entraining amount adjusting structure is arranged in the air intake bypass recirculation cavity.

Abstract: Provided are a display substrate, a preparation method thereof, and a display apparatus. The display substrate includes: a first display region and a second display region; the first display region includes a plurality of first pixels, the first pixel includes a passive light-emitting device, the second display region includes a plurality of second pixels, the second pixel includes an active light-emitting device and a pixel drive circuit electrically connected to the active light-emitting device. The first display region further includes a plurality of first cathode blockers, and the first cathode blocker includes at least one first groove, wherein the first cathode blocker is provided between at least two adjacent columns of first pixels, to make the cathodes of the two adjacent columns of first pixels disconnected.

Abstract: Music pushing method, apparatus, electronic device, and storage medium are provided by the embodiments of the present disclosure, for the method, firstly, a user end displays user information that satisfies a preset association relationship with music currently on a music playing interface in response to an operation acting on the music playing interface. In the present embodiments, upon inputting an operation instruction on target music by a user, information of other users who have taken an associated operation instruction to the target music and have an unrestricted friend relationship with the user is displayed, and by presenting music lists corresponding to other users, the user is guided to acquire music pushing information, and thus, ways for the user to acquire the music pushing information are expanded, and problems that music pushing is single and centralized as well as the pushing depends on a friend relationship are overcome.

Abstract: Instructions embedded on a computer-readable medium, when executed on one or more computer devices, improve video coding performance while using a merge mode in motion estimation. The instructions comprise instructions to perform one or more refinement searches on a plurality of candidate regions of a current frame. The instructions also comprise instructions to determine one or more distortion values based, at least in part, on reduced candidate regions and instructions to code motion data based, at least in part, on the one or more refinement searches.

Abstract: A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

Abstract: A temporal domain rate distortion optimization based on video content characteristic and QP-? correction provides the temporal domain rate distortion optimization based on the video content characteristic and the QP-? correction for a new generation encoder AV1, wherein according to a previous temporal domain dependency relationship under an HEVC-RA coding structure, a feature of the new generation encoder AV1 and a video sequence feature, an aggregation distortion of a current coding unit and an affected future coding unit is estimated and ta propagation factor of the current coding unit in a temporal domain distortion propagation model is calculated by constructing a temporal domain distortion propagation chain, wherein a Lagrange multiplier is adjusted through a more accurate propagation factor to realize a temporal domain dependency rate distortion optimization, and a relationship of QP-? is re-corrected and an I frame is adjusted to achieve a better coding effect.

Abstract: A temporal domain rate distortion optimization based on video content characteristic and QP-? correction provides the temporal domain rate distortion optimization based on the video content characteristic and the QP-? correction for a new generation encoder AV1, wherein according to a previous temporal domain dependency relationship under an HEVC-RA coding structure, a feature of the new generation encoder AV1 and a video sequence feature, an aggregation distortion of a current coding unit and an affected future coding unit is estimated and to propagation factor of the current coding unit in a temporal domain distortion propagation model is calculated by constructing a temporal domain distortion propagation chain, wherein a Lagrange multiplier is adjusted through a more accurate propagation factor to realize a temporal domain dependency rate distortion optimization, and a relationship of QP-? is re-corrected and an I frame is adjusted to achieve a better coding effect

Abstract: A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

Abstract: A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

Abstract: A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

Abstract: A method operates within an integrated circuit device having a plurality of processing lanes. The method determines a first number of packs among one or more first packs associated with a first processing lane of the plurality of processing lanes, associates the first number of packs with a first used field of the first processing lane, determines a second number of packs among one or more second packs associated with a second processing lane of the plurality of processing lanes, and associates the second number of packs with a second used field of the second processing lane.

Abstract: A method operates within an integrated circuit device having a plurality of processing lanes. The method determines a first number of packs among one or more first packs associated with a first processing lane of the plurality of processing lanes, associates the first number of packs with a first used field of the first processing lane, determines a second number of packs among one or more second packs associated with a second processing lane of the plurality of processing lanes, and associates the second number of packs with a second used field of the second processing lane.

Abstract: A method of operation within an integrated circuit device having a plurality of processing lanes. A first sub-stream of data, having a variable length, is generated in a first one of the processing lanes. A second sub-stream of data, also having a variable length, is generated in a second one of the processing lanes. The first and second sub-streams are then output to form a single bitstream.

Abstract: A method of encoding a block of data. A first plurality of data in the block of data is assigned a worth based on a first algorithm. A second plurality of data, which is lower in frequency than the first plurality of data, in the block of data is assigned a worth according to a second algorithm. The block of data is assigned a worth based on the worth of the first plurality of data and the second plurality of data. The worth of the block of data is then compared to a threshold value, and subsequently one or more data values of the block of data are adjusted based on the comparison.

Abstract: The error concealment technique disclosed herein relates to the use of existing information by the decoder to conceal bitstream errors regardless of what the encoder does. Examples of existing information include, for example, the previous reference frame, macroblock information for the previous reference frames, etc. Another aspect of the system described herein relates to the steps that the encoder can take to enhance the decoder's ability to recover gracefully from a transmission error. Exemplary steps that can be taken by the encoder include intra walk around and sending GOB headers. Although these encoder techniques can provide greatly enhanced results, they are not strictly necessary to the system described herein.