Patents by Inventor Yiping Szu

Yiping Szu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for characterizing an integrated circuit manufacturing process
    Patent number: 8091063
    Abstract: A system that characterizes an integrated circuit manufacturing process is presented. During operation, the system receives a layout which includes a plurality of test structures for semiconductor devices, wherein each test structure varies one or more design variables. The system then fabricates a plurality of wafers based on the layout, wherein each wafer in the plurality of wafers is fabricated using one of a plurality of process settings. Next, the system obtains performance characteristics for the plurality of test structures on the plurality of wafers. The system then generates a process model that is based on at least the effect that values for the one or more design variables and the plurality of process settings have on the performance characteristics of the plurality of test structures.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: January 3, 2012
    Assignee: Synopsys, Inc.
    Inventors: Mark Laird, Wayne Clark, Yiping Szu
  • METHOD AND APPARATUS FOR CHARACTERIZING AN INTEGRATED CIRCUIT MANUFACTURING PROCESS
    Publication number: 20100005436
    Abstract: A system that characterizes an integrated circuit manufacturing process is presented. During operation, the system receives a layout which includes a plurality of test structures for semiconductor devices, wherein each test structure varies one or more design variables. The system then fabricates a plurality of wafers based on the layout, wherein each wafer in the plurality of wafers is fabricated using one of a plurality of process settings. Next, the system obtains performance characteristics for the plurality of test structures on the plurality of wafers. The system then generates a process model that is based on at least the effect that values for the one or more design variables and the plurality of process settings have on the performance characteristics of the plurality of test structures.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 7, 2010
    Applicant: SYNOPSYS, INC.
    Inventors: Mark Laird, Wayne Clark, Yiping Szu