Abstract: The present disclosure provides a content input method, applied to a head mounted display device, which comprises a headphone apparatus, a display apparatus and a touch input apparatus. The method comprises steps of: controlling the display apparatus to display a soft keyboard input interface in response to a content input request, the soft keyboard input interface comprising an input box and a plurality of virtual keys arranged circularly; determining a virtual key to be input in response to a first touch action applied an annular first touch pad of the touch input apparatus; and displaying a character in the input box when the virtual key to be input is determined to be the character. The present disclosure further provides a head mounted display device. The head mounted display device and the content input method of the present disclosure can help the user to input after wearing the head mounted display device.

Abstract: A semiconductor device and its manufacturing method are presented. The semiconductor device includes a collection region, a base region adjacent to the collection region, an emission region adjacent to the base region, and a doped semiconductor layer on the emission region. The width of the doped semiconductor layer is larger than the width of the emission region, a conductive type (e.g., P-type or N-type) of the doped semiconductor layer is the same as a conductive type of the emission region. In this inventive concept, the width of the doped semiconductor layer on the emission region is larger than the width of the emission region, that equivalently increases the width of the emission region, which in turn increases the DC amplification factor (?) and therefore improves the overall performance of the semiconductor device.

Abstract: The present invention provides a method for assembling a camera module, including: arranging a first sub-lens assembly and a photosensitive assembly on an optical axis of a second sub-lens assembly to form an optical system capable of imaging; increasing an actual measured resolution of imaging of the optical system to a first threshold by adjusting a relative position of the first sub-lens assembly with respect to the second sub-lens assembly; decreasing an actual measured image plane inclination of imaging of the optical system, obtained by using the photosensitive element, to a second threshold by adjusting an angle of an axis of the photosensitive assembly with respect to a central axis of the second sub-lens assembly; and connecting the first sub-lens assembly, the second sub-lens assembly, and the photosensitive assembly. The present invention further provides a corresponding camera module.

Abstract: A pipe body, wherein the pipe body (10) has a welded portion (11) at both ends of the pipe body, aligned in a widthwise direction of the pipe body (10). The thickness of the welded portion (11) decreases gradually from the inside to the outside of the pipe, and an outer end of the welded portion (11) is located at a center portion of the pipe body (10) in a thickness direction. The configuration of the welding structure enhances the strength of the welded portion of the pipe, so that the pipe will not crack easily when it is reworked by flaring or bending, thus having high reworkability. In addition, a pipe (100) made of the pipe body (10) and a method of making the pipe (100) are disclosed.

Abstract: The present disclosure discloses a method for compensating for image quality of an optical system by means of a lens adjustment, applicable to a camera module comprising an adjustable lens or an adjustable lens set, the method comprising the following steps: (A) determining, based on imaging information of a to-be-adjusted optical system, parameters that need to be adjusted for compensating for the image quality; (B) establishing functions of relation between the parameters that need to be adjusted for compensating for the image quality and a to-be-adjusted lens factors; and (C) determining an adjustment mode and an adjustment amount for the to-be-adjusted lens based on the relation between the parameters that need to be adjusted for compensating for the image quality and the to-be-adjusted lens factors.

Abstract: A camera lens module includes a lens assembly. The lens assembly may comprise a first optical lens module comprising a first carrier and at least one first optical lens received in the first carrier; and a second optical lens module comprising a second carrier, at least one second optical lens received in the second carrier, and a bearing portion connected to the second carrier. When the first optical lens module and the second optical lens module are assembled together, an adjustable clearance exists between the first carrier and the bearing portion, and between bottom surfaces of the first carrier and a lowermost lens of the first optical lenses and a top surface of an uppermost lens of the second optical lenses.

Abstract: A display substrate, a display device and a method to identify a display device are provided. The display substrate comprises a display region and a periphery region. The periphery region comprises a plurality of first bonding pads electrically connected to metal wires disposed at the display region and a plurality of second bonding pads including at least two identification bonding pads. The at least two identification bonding pads are electrically connected to voltage-level signal lines respectively, and are labeled with identify information according to voltage-level signals provide by the voltage-level signal lines.

Abstract: A semiconductor device and its manufacturing method are presented. The semiconductor device includes a collection region, a base region adjacent to the collection region, an emission region adjacent to the base region, and a doped semiconductor layer on the emission region. The width of the doped semiconductor layer is larger than the width of the emission region, a conductive type (e.g., P-type or N-type) of the doped semiconductor layer is the same as a conductive type of the emission region. In this inventive concept, the width of the doped semiconductor layer on the emission region is larger than the width of the emission region, that equivalently increases the width of the emission region, which in turn increases the DC amplification factor (?) and therefore improves the overall performance of the semiconductor device.

Abstract: A display substrate, a display device and a method to identify a display device are provided. The display substrate comprises a display region and a periphery region. The periphery region comprises a plurality of first bonding pads electrically connected to metal wires disposed at the display region and a plurality of second bonding pads including at least two identification bonding pads. The at least two identification bonding pads are electrically connected to voltage-level signal lines respectively, and are labeled with identify information according to voltage-level signals provide by the voltage-level signal lines.

Abstract: A display substrate, a display device and a method to identify a display device are provided. The display substrate comprises a display region and a periphery region. The periphery region comprises a plurality of first bonding pads electrically connected to metal wires disposed at the display region and a plurality of second bonding pads including at least two identification bonding pads. The at least two identification bonding pads are electrically connected to voltage-level signal lines respectively, and are labeled with identify information according to voltage-level signals provide by the voltage-level signal lines.

Abstract: A display substrate, a display device and a method to identify a display device are provided. The display substrate comprises a display region and a periphery region. The periphery region comprises a plurality of first bonding pads electrically connected to metal wires disposed at the display region and a plurality of second bonding pads including at least two identification bonding pads. The at least two identification bonding pads are electrically connected to voltage-level signal lines respectively, and are labeled with identify information according to voltage-level signals provide by the voltage-level signal lines.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to educe a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Abstract: A memory read system includes a memory column having a plurality of dual port memory cells that are controlled by separate read word lines and a read bit line structure organized into upper and lower read bit line portions. Additionally, the memory read system also includes a pseudo-differential memory read unit coupled to the read bit line structure, wherein the upper and lower read bit line portions respectively control corresponding upper and lower local bit lines to provide a global bit line for the memory column. A method of reading a memory is also included.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Abstract: The present disclosure provides a device and method for storing encoded and/or decoded codes by re-using an encoder. The device and method for storing the encoded and/or decoded codes according to the present disclosure enables re-use of the encoder during a decoding process, which makes it unnecessary to use additional hardware and thereby reduces an area consumed by an EDAC (error detection and correction) decoder.