Patents by Inventor Yiqun Lin

Yiqun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112971
    Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Yiqun Bai, Dingying Xu, Srinivas Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Haobo Chen, Kyle Arrington, Bohan Shan
  • Publication number: 20240091495
    Abstract: A catheter reinforcement layer (100) and a catheter (10). The catheter reinforcement layer (100) includes a spring component (110) and at least one axial component (120). The at least one axial component (120) extends along the spring component (110) from a proximal end to a distal end, and has at least one intersection with the spring component (110). According to the catheter reinforcing layer (100), by introducing one or more axial components (120) into a reinforcing layer of an existing spring component (110), the axial modulus of the catheter (10) is increased, thereby avoiding axial deformation or even breakage of the tubular body of the catheter (10) due to axial force.
    Type: Application
    Filed: January 11, 2022
    Publication date: March 21, 2024
    Inventors: Heng LIN, Yunyun LIU, Yiqun Bruce WANG, Xueli LUO
  • Publication number: 20240071848
    Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Bohan SHAN, Haobo CHEN, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Bai NIE, Gang DUAN, Kyle ARRINGTON, Ziyin LIN, Hongxia FENG, Yiqun BAI, Xiaoying GUO, Dingying David XU, Jeremy D. ECTON, Kristof DARMAWIKARTA, Suddhasattwa NAD
  • Publication number: 20230415184
    Abstract: Disclosed in the application is a side-press switch water outlet apparatus for a shower, including a valve body, a water outlet panel, a switching piece, a ratchet and a driving unit. The valve body is provided with a water inlet channel; the water outlet panel is at least provided with a first water outlet channel and a second water outlet channel; the switching piece is rotatably arranged on the valve body, and the water inlet channel switches water supply between the first water outlet channel and the second water outlet channel through the switching piece; the ratchet is connected with the switching piece in a circumferential limit way. According to the solution, the key of the driving unit moves in the direction perpendicular to the shower handle, which is more in line with the use habits of a user and improves the user experience.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 28, 2023
    Applicant: Xiamen GSH Technology CO., LTD.
    Inventors: Sheng KONG, Yiqun LIN, Shaochun LIN
  • Publication number: 20200050692
    Abstract: Consistent read queries are enabled from a secondary compute node. In response to a read query, a page of data can be requested from a storage node with a first log sequence number indicating an update state of a local store of a compute node. The page of data can be received from the storage node with a second log sequence number indicating an update state of the page. Processing can be deferred until the first log sequence number is greater than or equal to the second log sequence number, wherein the first log sequence number is updated in response to automatic updates of the local store. A row of data can be retrieved from the page in accordance with the request. Further, a version of the row of data can be retrieved that has a timestamp equal to or before a timestamp associated with initiation of the read request.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Panagiotis Antonopoulos, Chaitanya Sreenivas Ravella, Yiqun Lin, Wei Chen, Girish Mittur Venkataramanappa, Hanumantha Rao Kodavalla
  • Patent number: 10245523
    Abstract: The present utility model provides a magnetic building block. A building block back side is installed on a rear end of a building block front side. Four notches are formed on both of the rear end of the building block front side and a front end of the building block back side. Four protruding chucks are formed on both of the rear end of the building block front side rear end and the front end of the building block back side. Four small magnets are disposed on the front end of the building block back side. The protruding chuck and the notch are disposed on two sides of the small magnet. An embedded paper is disposed between the building block front side and the building block back side. The embedded paper is inlaid in a rectangle surrounded by the notch, the small magnet, and the protruding chuck.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: April 2, 2019
    Assignee: Shantou Xinbida Early Education Technology Co., Ltd.
    Inventor: Yiqun Lin
  • Publication number: 20180333652
    Abstract: The present utility model provides a magnetic building block. A building block back side is installed on a rear end of a building block front side. Four notches are formed on both of the rear end of the building block front side and a front end of the building block back side. Four protruding chucks are formed on both of the rear end of the building block front side rear end and the front end of the building block back side. Four small magnets are disposed on the front end of the building block back side. The protruding chuck and the notch are disposed on two sides of the small magnet. An embedded paper is disposed between the building block front side and the building block back side. The embedded paper is inlaid in a rectangle surrounded by the notch, the small magnet, and the protruding chuck.
    Type: Application
    Filed: July 14, 2017
    Publication date: November 22, 2018
    Inventor: Yiqun LIN
  • Publication number: 20110269640
    Abstract: Nucleic acid probes for detecting kRas gene mutations, liquid chips and detection methods thereof are provided. The liquid chips for detecting kRas gene mutations comprise: microspheres coupled with wild-type and mutant-type probes, each of which is amino-substituted at 5?-terminal, specific for kRas codons 12, 13 and/or 61, and primers for amplifying the target sequence biotin-labeled at the terminal which are enriched with mutant alleles of kRas codons 12, 13 and/or 61 to be detected. The detection methods are rapid and accurate, and the processes of the methods are easy to perform. The liquid chip can be used to detect mutations of kRas as assistance to early diagnosis of pancreatic cancer, and can be used to prognose efficiency of the molecular targeted therapy to choose right medicine accurately clinically and avoiding economic loss and time loss caused by unnecessary treatment.
    Type: Application
    Filed: October 19, 2009
    Publication date: November 3, 2011
    Applicant: GUANGZHOU SUREXAM BIO-TECH CO., LTD.
    Inventors: Jiasen Xu, Shiyang Wu, Lifen Ren, Jiaying He, Huiyi Yang, Yiqun Lin
  • Patent number: 7310595
    Abstract: A method of determining electrical parameters of inductive elements includes a novel technique of inverting an impedance matrix representative of said inductive circuit element. The method reduces model simulation time by a factor of 3000. In one embodiment, simulation time of a device model was reduced from 1 hour to less than 3 seconds. The method is suitable for use with circuit element modeling tools, circuit simulation environments, and antenna modeling systems. The method may be applied to inductors, transformers, antennas, etc.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: December 18, 2007
    Assignee: Intersil Americas Inc.
    Inventors: Rex Lowther, Yiqun Lin
  • Patent number: 7110933
    Abstract: A method of a modeling metallization parasitics with the use of a simulation program. In one embodiment, a method of simulating interconnect lines in an electronic design automation simulation is disclosed. The method comprises partitioning the interconnect lines into groups of interconnect lines. Each group of interconnect lines does not have interactions with any of the other groups of interconnect lines. Moreover, at least one of the groups of interconnect lines contains at least three interconnect lines. The interconnect lines in each group are modeled. The modeling includes at least one of modeling mutual inductances and modeling of mutual capacitances.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: September 19, 2006
    Assignee: Intersil Americas Inc.
    Inventors: Rex E. Lowther, Gregg D. Croft, Yiqun Lin, Robert Lomenic, James P. Furino, Jr., Joseph A. Czagas
  • Publication number: 20050055650
    Abstract: Methods of filling empty areas in a layout simulation. In one embodiment, a method of simulating an integrated circuit layout is disclosed. The method comprises automatically identifying empty areas in a layout that can be filled and generating fill patterns to fill the empty areas.
    Type: Application
    Filed: September 5, 2003
    Publication date: March 10, 2005
    Inventors: Yiqun Lin, Jeffrey Shoemaker
  • Publication number: 20050038639
    Abstract: A circuit simulation and analysis tool for analyzing circuit parameters. In one embodiment, a method of evaluating circuit parameters of an integrated circuit design is disclosed. The method comprises defining two or more variables to apply to the circuit parameters and running a simulation with the two or more variables on the circuit parameters.
    Type: Application
    Filed: August 15, 2003
    Publication date: February 17, 2005
    Inventor: Yiqun Lin
  • Publication number: 20050027502
    Abstract: A method of a modeling metallization parasitics with the use of a simulation program. In one embodiment, a method of simulating interconnect lines in an electronic design automation simulation is disclosed. The method comprises partitioning the interconnect lines into groups of interconnect lines. Each group of interconnect lines does not have interactions with any of the other groups of interconnect lines. Moreover, at least one of the groups of interconnect lines contains at least three interconnect lines. The interconnect lines in each group are modeled. The modeling includes at least one of modeling mutual inductances and modeling of mutual capacitances.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 3, 2005
    Inventors: Rex Lowther, Gregg Croft, Yiqun Lin, Robert Lomenic, James Furino, Joseph Czagas
  • Publication number: 20050028113
    Abstract: A translation tool for the design of integrated circuits. In one embodiment, a method comprises translating select device parameters in a first database associated with a first process to device parameters in a second database associated with a second process and displaying a design based on the device parameters in the second database.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 3, 2005
    Inventors: Yiqun Lin, Jeffrey Shoemaker
  • Publication number: 20040225485
    Abstract: A method of determining electrical parameters of inductive elements includes a novel technique of inverting an impedance matrix representative of said inductive circuit element. The method reduces model simulation time by a factor of 3000. In one embodiment, simulation time of a device model was reduced from 1 hour to less than 3 seconds. The method is suitable for use with circuit element modeling tools, circuit simulation environments, and antenna modeling systems. The method may be applied to inductors, transformers, antennas, etc.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 11, 2004
    Applicant: Intersil Americas Inc.
    Inventors: Rex Lowther, Yiqun Lin
  • Patent number: 6775807
    Abstract: A method of determining electrical parameters of inductive elements includes a novel technique of inverting an impedance matrix representative of said inductive circuit element. The method reduces model simulation time by a factor of 3000. In one embodiment, simulation time of a device model was reduced from 1 hour to less than 3 seconds. The method is suitable for use with circuit element modeling tools, circuit simulation environments, and antenna modeling systems. The method may be applied to inductors, transformers, antennas, etc.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: August 10, 2004
    Assignee: Intersil Americas Inc.
    Inventors: Rex Lowther, Yiqun Lin
  • Publication number: 20040034837
    Abstract: A method of determining electrical parameters of inductive elements includes a novel technique of inverting an impedance matrix representative of said inductive circuit element. The method reduces model simulation time by a factor of 3000. In one embodiment, simulation time of a device model was reduced from 1 hour to less than 3 seconds. The method is suitable for use with circuit element modeling tools, circuit simulation environments, and antenna modeling systems. The method may be applied to inductors, transformers, antennas, etc.
    Type: Application
    Filed: August 19, 2002
    Publication date: February 19, 2004
    Inventors: Rex E. Lowther, Yiqun Lin