Patents by Inventor Yire Zine Lee

Yire Zine Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6313413
    Abstract: The substrate of the present invention mainly includes a plurality of bonding pads, a plurality of ball pads, a plurality of traces, a plurality of holes, a first wire and a second wire. The bonding pads and ball pads are located on a first surface of the substrate and are connected to one another by the traces. The first wire is arranged at the edge of the first surface of the substrate, the second wire is arranged at a slot area of a second surface of the substrate which is adhesively covered by a solder mask and further has two ends connecting to the first wire. The holes connect the first surface to the second surface. The traces are connected the bonding pads and ball pads of the first surface by passing through the corresponding holes and a slot area to the second wire of the second surface to form closed loops. In the slot area, the solder mask adhesively covers the traces.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: November 6, 2001
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kun-Ching Chen, Yire-Zine Lee, Yung-I Yeh, Su Tao
  • Patent number: 6204559
    Abstract: This invention moves at least one outer via outwardly to a location under the edge of the chip so as to form an offset via. Since the via is made of copper, the offset via provides sufficient supporting strength for the chip edge during molding process. Further, this invention also disposes a copper mesh on the substrate at the area without vias and traces so as to enhance the substrate strength for supporting the chip. According to another aspect of this invention, dummy via holes are provided for the substrate at the area under the chip edge for supporting the chip. Since the copper mesh, offset via, the dummy via hole are made of copper having sufficient supporting strength for the chip, the crack problem during molding process can be eliminated.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: March 20, 2001
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun Hung Lin, Yire Zine Lee, Su Tao, Jian Wen Chen