Abstract: One embodiment of the present invention capable of decommissioning a defective non-volatile memory (“NVM”) page in a block is disclosed. A process able to logically decommission a defective page is able to detect defective or bad pages while executing a write operation writing information to one or more NVM page in a NVM block. For example, after examining operation status after completion of the write operation, the NVM page is identified as a defective page if the operation status fails to meet a set of predefined conditions under a normal write operation. Upon marking a location of a page status table to indicate the NVM page as defective page, the page status table containing the page defective information associated with the NVM page is stored at a predefined page in the NVM block.

Abstract: A computing system includes: storage devices configured to read data sectors; and a data correction engine, coupled to the storage devices, configured to: detect an error data sector among the data sectors, generate soft information from the error data sector, apply a soft bit flipping logic to the error data sector to produce a transformed data sector, and generate a corrected data sector from the transformed data sector.

Abstract: A method and system for enabling Non-Volatile Memory express (NVMe) for accessing remote solid state drives (SSDs) (or other types of remote non-volatile memory) over the Ethernet or other networks. An extended NVMe controller is provided for enabling CPU to access remote non-volatile memory using NVMe protocol. The extended NVMe controller is implemented on one server for communication with other servers or non-volatile memory via Ethernet switch. The NVMe protocol is used over the Ethernet or similar networks by modifying it to provide a special NVM-over-Ethernet frame.

Abstract: A method for processing a trim command via an input and output (“I/O”) command of a solid-state drive (“SSD”) using various tables is disclosed. The process is able to retrieve a trim node state table (“TNST”) from a local memory in response to the trim command. Upon identifying current node status of the TNST associated with a logical block address (“LBA”) referenced by the trim command, a trim operation is processed to a node if the current node status indicates a pending state. After changing the node status to a dirty state when the current node status is in a clean state, the content of a trim invalid bitmap table (“TIBT”) is updated to indicate the status of LBAs when the current node status is in a dirty state.

Abstract: The power protection system includes a host driver in the host system and an SSD driver situated in an SSD. In one aspect, the host driver includes a write buffer able to store information during a write operation to an open-channel solid state drive (“OCSSD”). The SSD driver connected to the host driver via a bus includes an SSD double data rate (“DDR”) buffer configured to store a copy of content similar to content in the write buffer and an SSD nonvolatile memory (“NVM”) coupled to the SSD DDR buffer and configured to preserve the data stored in the SSD DDR buffer when a power failure is detected. The SSD driver also includes a power supply, which can be a capacitor, coupled to the SSD DDR buffer for providing power to the SSD DDR buffer when the power is lost.

Abstract: A computing system includes: a data block including data pages and each of the data pages includes data sectors and each of the data sectors include sector data and a sector redundancy; a storage engine, coupled to the data block, configured to: apply a first protection across the data pages, apply a second protection across the data sectors, and correct at least one of the data sectors when a sector correction with the sector redundancy failed with the first protection and the second protection.

Abstract: A computing system includes: an interface circuit configured to provide access to a data block including an arrangement of multiple individual data; and a processing circuit, coupled to the interface circuit, configured to generate a non-orthogonal protection data corresponding to instances of the individual data along a non-orthogonal direction within the data block for correcting the one or more of the corresponding instances of the individual data.

Abstract: A system configuration containing a host, solid state drive (“SSD”), and controller able to perform a hybrid mode non-volatile memory (“NVM”) access is disclosed. Upon receiving a command with a logical block address (“LBA”) for accessing information stored in NVM, a secondary flash translation layer (“FTL”) index table is loaded to a first cache and entries in a third cache is searched to determine validity associated with stored FTL table. When the entries in the third cache are invalid, the FTL index table in the second cache is searched to identify valid FTL table entries. If the second cache contains invalid FTL index table, a new FTL index table is loaded from NVM to the second cache. The process subsequently loads at least a portion of FTL table indexed by the FTL index table in the third cache.

Abstract: One embodiment of the present invention discloses a process of low latency non-volatile memory access using various approaches. In one aspect, a process for low latency memory access to a non-volatile memory (“NVM”) of a solid state drive (“SSD”) is able to generate a submission queue entry (“SQE”) for an SSD memory access by a host to a connected SSD. Upon pushing the SQE from the host to a submission queue (“SQ”) viewable by a controller of the SSD, the counter value of an SQ header pointer is incremented to reflect storage of the first SQE in the SQ. After detecting the SQE in the SQ by a snooping component in the memory controller in accordance with the SQ header pointer, the SQE is fetched from the SQ by the controller and one or more SSD memory instructions are subsequently executed in response to content of the SQE.

Abstract: A computing system includes: a control circuit configured to: determine a user data, generate a base set including a base protection data based on encoding the user data according to a coding mechanism, generate an extra protection data based on encoding the user data differently from the base set according to the coding mechanism; and a storage circuit configured to store the extra protection data corresponding to the base set. The computing system can further include: an storage circuit configured to: provide a received codeword corresponding to a user data and a base protection data, provide an extra protection data corresponding to the received codeword; a control circuit configured to: decode the received codeword according to a coding mechanism, and further decode the received codeword to recover the user data based on decoding differently from decoding the base set and using the extra protection data according to the coding mechanism.

Abstract: A method and system for enabling Non-Volatile Memory express (NVMe) for accessing remote solid state drives (SSDs) (or other types of remote non-volatile memory) over the Ethernet or other networks. An extended NVMe controller is provided for enabling CPU to access remote non-volatile memory using NVMe protocol. The extended NVMe controller is implemented on one server for communication with other servers or non-volatile memory via Ethernet switch. The NVMe protocol is used over the Ethernet or similar networks by modifying it to provide a special NVM-over-Ethernet frame.

Abstract: A method and/or apparatus capable of storing information in non-volatile memory with multiple namespaces is disclosed. The method or apparatus, in one aspect, includes a translation table, a global LBA table, and a FTL table wherein the translation table is also known as namespace translation table. The translation table, in one example, includes multiple entries wherein each entry stores translated information relating to translation between an incoming logical block address (“LBA”) with namespace identifiers (“NSIDs”) and a translated LBA (“TR_LBA”). The global LBA table, in one aspect, has multiple global entries, wherein each global entry stores a global LBA base unit generated in response to a TR_LBA. The FTL table contains multiple FTL entries, wherein each FTL entry includes a physical page address (“PPA”) indexed by a global LBA base unit. The apparatus is capable of facilitating memory access based on the PPA.

Abstract: An improved garbage collection (“GC”) process configured to recover new blocks from used storage space is disclosed. After initiating the GC process for a flash memory in accordance with at least one of predefined triggering events, a first valid page within a first block marked as an erasable block is identified. Upon determining a first signature representing the content of the first valid page according to a predefined signature generator, the process identifies a second valid page within a second block as a duplicated page of the first valid page in response to the first signature. The process subsequently associates the logical block address (“LBA”) of the first valid page to the second valid page. In an alternative embodiment, page compression and sequential order of page arrangement can also be implemented to further enhance efficiency of garbage collection.

Abstract: One embodiment of the present invention discloses a shared non-volatile memory (“NVM”) system using a distributed flash translation layer (“FTL”) scheme capable of facilitating data storage between multiple hosts and NVM devices. A process of shared NVM system includes an NVM management module or memory controller able to receive a request from a host for reserving a write ownership. The write ownership allows a host to write information to a portion of storage space in an NVM device. Upon identifying availability of the write ownership associated with the NVM device in accordance with a set of predefined policy stored in the NVM management module, the request is granted to the host if the write ownership is available. The host is subsequently allowed to fetch the FTL snapshot from the NVM device for the write operation.

Abstract: A computing system includes: a control circuit configured to: determine a user data, generate a base set including a base protection data based on encoding the user data according to a coding mechanism, generate an extra protection data based on encoding the user data differently from the base set according to the coding mechanism; and a storage circuit configured to store the extra protection data corresponding to the base set. The computing system can further include: an storage circuit configured to: provide a received codeword corresponding to a user data and a base protection data, provide an extra protection data corresponding to the received codeword; a control circuit configured to: decode the received codeword according to a coding mechanism, and further decode the received codeword to recover the user data based on decoding differently from decoding the base set and using the extra protection data according to the coding mechanism.

Abstract: An improved garbage collection (“GC”) process configured to recover new blocks from used storage space is disclosed. After initiating the GC process for a flash memory in accordance with at least one of predefined triggering events, a first valid page within a first block marked as an erasable block is identified. Upon determining a first signature representing the content of the first valid page according to a predefined signature generator, the process identifies a second valid page within a second block as a duplicated page of the first valid page in response to the first signature. The process subsequently associates the logical block address (“LBA”) of the first valid page to the second valid page. In an alternative embodiment, page compression and sequential order of page arrangement can also be implemented to further enhance efficiency of garbage collection.

Abstract: A computing system includes: storage devices configured to read data sectors; and a data correction engine, coupled to the storage devices, configured to: detect an error data sector among the data sectors, generate soft information from the error data sector, apply a soft bit flipping logic to the error data sector to produce a transformed data sector, and generate a corrected data sector from the transformed data sector.

Abstract: A method and system for providing a dual memory access to a non-volatile memory device using expended memory addresses are disclosed. The digital processing system such as a computer includes a non-volatile memory device, a peripheral bus, and a digital processing unit. The non-volatile memory device such as a solid state drive can store data persistently. The peripheral bus, which can be a peripheral component interconnect express (“PCIe”) bus, is used to support memory access to the non-volatile memory device. The digital processing unit such as a central processing unit (“CPU”) is capable of accessing storage space in the non-volatile memory device in accordance with an extended memory address and offset.

Abstract: A computing system includes: an interface circuit configured to provide access to a data block including an arrangement of multiple individual data; and a processing circuit, coupled to the interface circuit, configured to generate a non-orthogonal protection data corresponding to instances of the individual data along a non-orthogonal direction within the data block for correcting the one or more of the corresponding instances of the individual data.

Abstract: One embodiment of the present invention capable of decommissioning a defective non-volatile memory (“NVM”) page in a block is disclosed. A process able to logically decommission a defective page is able to detect defective or bad pages while executing a write operation writing information to one or more NVM page in a NVM block. For example, after examining operation status after completion of the write operation, the NVM page is identified as a defective page if the operation status fails to meet a set of predefined conditions under a normal write operation. Upon marking a location of a page status table to indicate the NVM page as defective page, the page status table containing the page defective information associated with the NVM page is stored at a predefined page in the NVM block.