Patents by Inventor Yirn-Sheng Pan

Yirn-Sheng Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6092000
    Abstract: A method for maximizing the throughput of a multiple-step workstation in a plant includes forming an interrecipe delay time array having rows of delay times for a plurality of lots L.sub.n with a plurality of recipes R.sub.n caused by a lot L.sub.n-1 with a recipe R.sub.n-1 for n=1 to a, and columns of delay times for a recipe LR.sub.n caused by a plurality of recipes LR.sub.n-1 for n=1 to a. An array of feasible recipe-to-recipe sequences S(n,m) is then formed having rows of feasible recipe-to-recipe sequences for the lot L.sub.n in a plurality of orders O.sub.m for m=1 to a, and columns of feasible recipe-to-recipe sequences for a plurality of lots L.sub.n in the order O.sub.m for m=1 to a. A recipe-to-recipe sequence in an order that is selected to be processed has a value of 1, and all other sequences in that order have a value of 0. Subsequently, a lot-recipe mapping array is formed that maps a recipe to be used for each lot.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: July 18, 2000
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chun-Yen Kuo, Yirn-Sheng Pan, Horng-Huei Tseng
  • Patent number: 5960417
    Abstract: A computer system for determining the costing of the manufacturing process for a product. The computer system includes the combination of a data base computer and a manufacturing cost computer, the cost computer including a central processor, a memory, and a direct access storage device with tables of data including a product mix table, an equipment table, an overhead table, a direct material table, a direct material standard usage table, and a rework table, the system for preparing data for use in costing, calculating hourly rates for a part, calculating final costs for a part; and calculating part costs for a part.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: September 28, 1999
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yirn-Sheng Pan, Horng-Huei Tseng, Jeng-Tyan Lin
  • Patent number: 5950170
    Abstract: A method to maximize throughput of a group of multi-process machines whereby the number of each kind machine is determined. Then, the machine assignment of each machine is assigned a variable. Next, the throughput definition for each machine is calculated from a database of past production runs. Next, the capacity of each process is calculated. Then, the constraints of the machine assignment variables are determined. A linear programming model is then derived for the system. The linear programming model is then executed under the constraints to determine optimal machine assignments to maximize the capacity of the minimum capacity process.
    Type: Grant
    Filed: April 11, 1997
    Date of Patent: September 7, 1999
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yirn-Sheng Pan, Horng-Huei Tseng
  • Patent number: 5940298
    Abstract: A process is provided for operating a manufacturing plant subsequent to preventative maintenance steps. The steps of the process are the following. Provide a data processing system having memory means for data storage. Provide central processing means for (a) accessing data from the memory means, (b) receiving data from data input means and (c) supplying data to the memory means. Provide Preventive Maintenance (PM) Duration (D) data to the data processing system. Calculate the effect of a PM schedule upon the efficiency of operation of the plant. Provide a new PM schedule to improve the efficiency of operation of the plant.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: August 17, 1999
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yirn-Sheng Pan, Horng-Huei Tseng, Chun-Yen Kuo, Jeng-Tyan Lin
  • Patent number: 5889673
    Abstract: In dynamic dispatching of integrated circuit wafer lots in an integrated circuit fabrication plant, determine the Stage Achievement Rate (SAR) of descendant stages for each candidate stage to be processed by the fabrication plant. With the loading of descendant stages for each candidate stage, determine the Adjusted Loading (AL), where AL=SAR*(Loading of descendant stages for each candidate stage). Determine the Picked Probability (PP) equal to Normalized 1/AL of grouped descendant stages. Determine the Estimated Loading (EL) of descendant stages for each candidate stage. Determine the Estimated Achievement Rate (EAR) of descendant stages for each candidate stage. Next, determine the Estimated Adjusted Loading (EAL) of descendant stages for each candidate stage. Then determine the Total Estimated Adjusted Loading (TEAL) for each candidate stage. Finally, determine the Dynamic Dispatching Order (DDO) of the wafer lots.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: March 30, 1999
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yirn-Sheng Pan, Horng-Huei Tseng
  • Patent number: 5838565
    Abstract: A method of operating a batch sequential machine in a manufacturing plant to optimize processing of lots of work through a plurality of series of processing stations which perform various functions comprising the following steps. Collect interval-times (I.sub.i,j) for processing of lots through individual processing stations. Form a matrix of reduced times for processing lots through the processing stations. Determine permutations of the reduced times for a series of combinations of the processing stations for performing required processing tasks. Select the combination of interval-times providing the maximum reduction of total processing time.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: November 17, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hung-Ming Hsieh, Yirn-Sheng Pan, Horng-Huei Tseng
  • Patent number: 5748478
    Abstract: A method of output management of processing in a manufacturing plant with a plurality of stages during a running period. The method begins with the step of determining the stage In Flow of Work In Process (WIP) in the plant, determining the Out Flow of WIP in the plant, and calculating Flow Intensity of the plant, followed by calculating the equipment Capacity of the plant. The next steps are to calculate Equipment Capacity allocation of the plant, determine the bottleneck Stage Capacity of stages in the plant, determine the Rolling Output of the plant, followed by calculation of the Remaining Work In Process of the plant. Data on the Daily Output is collected. Remaining Work In Process is duplicated as Initial WIP for the next day. Testing is made to determine whether the running period has ended, and until the running period has ended, the method repeatedly loops back to the In Flow step.
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: May 5, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yirn-Sheng Pan, Horng-Huei Tseng