Abstract: A digital polar amplifier includes an amplitude control portion, comprising a plurality of amplitude driver cells, the plurality of amplitude driver cells comprising a first subset of amplitude driver cells and a second subset of amplitude driver cells; wherein the amplitude control portion is configured to: receive an input signal; selectively activate one or more amplitude driver cells from the first subset and/or the second subset based on an amplitude control code; and control each of the selectively activated one or more amplitude driver cells to output an amplitude output signal corresponding to the input signal; and wherein each amplitude driver cell in the first subset is configured to generate a respective amplitude output signal at a first power level, and wherein each amplitude driver cell in the second subset is configured to generate a respective amplitude output signal at a second power level, lower than the first power level.

Abstract: A digital power amplifier (DPA) architecture addresses power efficiency limitations in shared PA designs supporting multiple communication protocols with differing transmission power requirements. The DPA comprises PA cell arrays, with each cell including both low voltage (LV) and high voltage (HV) domain PA cells that are separately activated. For low power transmissions, LV domain cells operate while HV domain cells are placed into a high-impedance state to minimize loading and improve efficiency. For high power transmissions, both LV and HV domain cells operate to achieve desired transmit power. The architecture includes a unified combiner coupling both voltage domains, domain-specific output stages optimized for respective voltage levels, and a differential level shifter providing amplitude-preserving voltage conversion for HV domain control.

Abstract: For example, an apparatus may include an input to receive an input signal in a first voltage domain; a multi-mode power amplifier switchable between a plurality of power modes to generate an output signal based on the input signal; and an output to provide the output signal. For example, the multi-mode power amplifier may be configured to provide the output signal in the first voltage domain at a first power mode, and to provide the output signal in a second voltage domain at a second power mode. For example, a maximal voltage of the second voltage domain may be at least two times a maximal voltage of the first voltage domain.

Abstract: Techniques are disclosed to instruct how a switched capacitor digital power amplifier (PA) is configured to operate using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg. The digital PA has a topology that comprises a dual-feedback capacitive path that comprises a capacitive divider and a voltage stabilizing feedback path to selectively couple the capacitive divider to DC bias voltages.

Abstract: A digital to time convertor includes a frequency division stage, configured to generate a first frequency output based on a first instruction set and a second frequency output based on a second instruction set; a delay stage, configured to generate a first delayed frequency output and a second delayed frequency output based on the first frequency output, and to generate a third delayed frequency output and a fourth delayed frequency output based on the second frequency output; a selection stage, configured to output one of the first delayed frequency output or the third delayed frequency output based on a control code; and to output one of the second delayed frequency output, the second frequency output, the first frequency output, or the fourth delayed frequency output based on the control code; and a signal generator, configured to generate an interpolated signal based on the output of the selection stage.

Abstract: An apparatus may include: a first edge interpolator stage including: a first edge interpolator configured to interpolate, based on a phase modulation code, a first and second signal to generate a first edge interpolated signal comprising a first edge in a time domain between edges of the first and second signal; a second edge interpolator configured to interpolate, based on the phase modulation code, the first and second signal to generate a second edge interpolated signal comprising a second edge in the time domain between edges of the first and second signal; and a second edge interpolator stage configured to: receive the first edge interpolated signal and the second edge interpolated signal; and generate, based on the phase modulation code, a third edge interpolated signal comprising a third edge in the time domain between the edges of the first edge interpolated signal and the second edge interpolated signal.

Abstract: A transistor device can include a drain contact operably connected to a drain finger and a source contact operably connected to a source finger. The transistor device can further include diffusion area connected to the drain finger and the source finger to provide current to the drain finger and the source finger. The drain finger can have a length extending along an axis and different drain finger widths along the drain finger length such that current density is equal at each point along the drain finger length. The source finger can have a length extending along the axis and source finger widths along the source finger length such that current density is equal at each point along the source finger length.

Abstract: For example, an apparatus may include an input to receive an input signal in a first voltage domain; a multi-mode power amplifier switchable between a plurality of power modes to generate an output signal based on the input signal; and an output to provide the output signal. For example, the multi-mode power amplifier may be configured to provide the output signal in the first voltage domain at a first power mode, and to provide the output signal in a second voltage domain at a second power mode. For example, a maximal voltage of the second voltage domain may be at least two times a maximal voltage of the first voltage domain.

Abstract: Techniques are disclosed to instruct how a switched capacitor digital power amplifier (PA) is configured to operate using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg. The digital PA has a topology that comprises a dual-feedback capacitive path that comprises a capacitive divider and a voltage stabilizing feedback path to selectively couple the capacitive divider to DC bias voltages.