Abstract: A shift register unit circuit, a driving method thereof, a scanning drive circuit and a display panel are provided. The shift register unit circuit includes an input sub-circuit configured to set a level at a first node to be an effective level when an input terminal is at an effective level; at least two transmission sub-circuits configured to set a level at a coupled output control node to be an effective level when the first node is at the effective level; and at least two output sub-circuits, each of which is configured to conduct a coupled first clock signal terminal to a coupled output terminal when the coupled output control node is at an effective level.

Abstract: This disclosure discloses a shift register element, a method for driving the same, a gate driver circuit, and a display device. The shift register element comprises a first input circuit, a second input circuit, a first node control circuit, a second node control circuit, a third node control circuit, and N output circuits, where the first input circuit, the second input circuit, and the first node control circuit are configured to control a first node, the second node control circuit is configured to control a second node so that the third node control circuit controls the third node according to the first node and the second node, and the N output circuits control corresponding output terminals according to corresponding clock signal terminals under the control of the first node.

Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.

Abstract: A shift register unit circuit, a driving method thereof, a scanning drive circuit and a display panel are provided. The shift register unit circuit includes an input sub-circuit configured to set a level at a first node to be an effective level when an input terminal is at an effective level; at least two transmission sub-circuits configured to set a level at a coupled output control node to be an effective level when the first node is at the effective level; and at least two output sub-circuits, each of which is configured to conduct a coupled first clock signal terminal to a coupled output terminal when the coupled output control node is at an effective level.

Abstract: A gate driving sub-circuit, a driving method and a gate driving circuit are provided. The gate driving sub-circuit includes an input signal end, a shift signal output end, an inverted phase shift signal output end, a positive phase shift clock signal input end, an inverted phase shift clock signal input end, a first control clock signal input end, a second control clock signal input end, a first gate driving signal output end, a second gate driving signal output end, a shift register circuit and a control output circuit. The control output circuit includes a first control output sub-circuit and a second control output sub-circuit.

Abstract: This disclosure discloses a shift register element, a method for driving the same, a gate driver circuit, and a display device. The shift register element comprises a first input circuit, a second input circuit, a first node control circuit, a second node control circuit, a third node control circuit, and N output circuits, where the first input circuit, the second input circuit, and the first node control circuit are configured to control a first node, the second node control circuit is configured to control a second node so that the third node control circuit controls the third node according to the first node and the second node, and the N output circuits control corresponding output terminals according to corresponding clock signal terminals under the control of the first node.

Abstract: A source driving sub-circuit includes a shift register circuit and a latch circuit. The latch circuit includes a resetter and a latch. The resetter is coupled to an enabling signal terminal, a reset signal terminal and the latch. The latch is coupled to the shift register circuit and a data signal terminal. The latch is configured to receive signals output from the shift register circuit and at least in response to the signals output from the shift register circuit. And the resetter is configured to receive a signal provided from the enabling signal terminal and a signal provided from the reset terminal, and reset the at least one data signal latched by the latch in response to the signal provided from the enabling signal terminal.

Abstract: A pixel circuit and a display device are provided. The pixel circuit includes: a first inverter circuit having an input terminal connected to a first node and an output terminal connected to a second node; a second inverter circuit having an input terminal connected to the second node and an output terminal connected to a third node; a first switching circuit configured to disconnect a connection between the first node and the third node when a first scanning signal is at an active level; and a control circuit configured to control a level of at least one of the first node and the second node according to a level control signal when the first scanning signal is at an active level. Based on this, it can help to avoid the output signal abnormality of the latch inside the pixel and enhance the working stability of the pixel circuit.

Abstract: A shift register unit, a driving method, a gate driving circuit and a display device are provided. The shift register unit includes: an input circuit used to provide a pull-up node with a first control signal from a first control signal terminal; N output circuits, wherein an i-th output circuit is used to provide an i-th output terminal with an i-th clock signal from an i-th clock signal terminal; a pull-down control circuit used to provide a pull-down node with a first power source signal from a first power source terminal, and to provide the pull-down node with a second power source signal from a second power source terminal; and a pull-down circuit used to provide each output terminal and the pull-up node with the second power source signal.

Abstract: A source driving sub-circuit includes a shift register circuit and a latch circuit. The latch circuit includes a resetter and a latch. The resetter is coupled to an enabling signal terminal, a reset signal terminal and the latch. The latch is coupled to the shift register circuit and a data signal terminal. The latch is configured to receive signals output from the shift register circuit and at least in response to the signals output from the shift register circuit. And the resetter is configured to receive a signal provided from the enabling signal terminal and a signal provided from the reset terminal, and reset the at least one data signal latched by the latch in response to the signal provided from the enabling signal terminal.

Abstract: A gate driving sub-circuit, a driving method and a gate driving circuit are provided. The gate driving sub-circuit includes an input signal end, a shift signal output end, an inverted phase shift signal output end, a positive phase shift clock signal input end, an inverted phase shift clock signal input end, a first control clock signal input end, a second control clock signal input end, a first gate driving signal output end, a second gate driving signal output end, a shift register circuit and a control output circuit. The control output circuit includes a first control output sub-circuit and a second control output sub-circuit.

Abstract: A shift register unit, a driving method, a gate driving circuit and a display device are provided. The shift register unit includes: an input circuit used to provide a pull-up node with a first control signal from a first control signal terminal; N output circuits, wherein an i-th output circuit is used to provide an i-th output terminal with an i-th clock signal from an i-th clock signal terminal; a pull-down control circuit used to provide a pull-down node with a first power source signal from a first power source terminal, and to provide the pull-down node with a second power source signal from a second power source terminal; and a pull-down circuit used to provide each output terminal and the pull-up node with the second power source signal.

Abstract: The present application provides an array substrate and a method of manufacturing the same. The array substrate includes a first substrate having a drain electrode protruding from a side of the first substrate; a planarization layer at the side of the first substrate where the drain electrode protrudes, the planarization layer being provided with a stepped hole on the drain electrode, and a diameter of the stepped hole decreasing along a direction from a side of the planarization layer facing away the first substrate towards a side of the planarization layer facing the first substrate; a pixel electrode at the stepped hole and connected with the drain electrode; a passivation layer covering the planarization layer and the pixel electrode; and a common electrode on the passivation layer.

Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.

Abstract: A pixel circuit and a display device are provided. The pixel circuit includes: a first inverter circuit having an input terminal connected to a first node and an output terminal connected to a second node; a second inverter circuit having an input terminal connected to the second node and an output terminal connected to a third node; a switching circuit configured to disconnect a connection between the first node and the third node when a first scanning signal is at an active level; and a control circuit configured to control a level of at least one of the first node and the second node according to a level control signal when the first scanning signal is at an active level. Based on this, it can help to avoid the output signal abnormality of the latch inside the pixel and enhance the working stability of the pixel circuit.

Abstract: A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.

Abstract: The present application provides an array substrate and a method of manufacturing the same. The array substrate includes a first substrate having a drain electrode protruding from a side of the first substrate; a planarization layer at the side of the first substrate where the drain electrode protrudes, the planarization layer being provided with a stepped hole on the drain electrode, and a diameter of the stepped hole decreasing along a direction from a side of the planarization layer facing away the first substrate towards a side of the planarization layer facing the first substrate; a pixel electrode at the stepped hole and connected with the drain electrode; a passivation layer covering the planarization layer and the pixel electrode; and a common electrode on the passivation layer.

Abstract: A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.