Abstract: The present disclosure relates to the technical field of semiconductor integrated circuits and discloses a multi-mode array structure for in-memory computing, and a chip, including: an array of memory cells, function lines corresponding to all the memory cells measured by rows in the array of memory cells, and complementary function lines and bit lines BL corresponding to all the memory cells measured by columns in the array of memory cells. According to the present disclosure, the TCAM function and CNN and SNN operations are enabled; the multi-mode array for in-memory computing herein goes beyond the limits of the von Neumann architecture by integrating the multiple modes of storage and computation, achieving efficient operation and computation; in addition to solving the computing power problem, a new array mode is provided to promote the development of high-integration circuits.

Abstract: Disclosed is a low-power and compact neuron circuit implementing a ReLU activation function including a first-layer synaptic array, a neuron transistor, a resistor, and a second-layer synaptic array. The neuron transistor is a MOS transistor having a threshold voltage-adjustable property, a gate electrode of the neuron transistor is connected to each voltage output end of the first-layer synaptic array, and a drain electrode of the neuron transistor is connected to each voltage input end of the second-layer synaptic array. Thus, it is possible to satisfy the decision computation and output of different synaptic array output values by adjusting the magnitude of the threshold voltage of the transistor. The neuron circuit requires only one transistor in cooperative connection with the first-layer synaptic array and the second-layer synaptic array to implement the ReLU activation function; therefore, a significant improvement is achieved in terms of energy efficiency, delay reduction, and space utilization.

Abstract: The present disclosure relates to the technical field of semiconductor integrated circuits and discloses a multi-mode array structure for in-memory computing, and a chip, including: an array of memory cells, function lines corresponding to all the memory cells measured by rows in the array of memory cells, and complementary function lines and bit lines BL corresponding to all the memory cells measured by columns in the array of memory cells. According to the present disclosure, the TCAM function and CNN and SNN operations are enabled; the multi-mode array for in-memory computing herein goes beyond the limits of the von Neumann architecture by integrating the multiple modes of storage and computation, achieves efficient operation and computation; in addition to solving the computing power problem, a new array mode is provided to promote the development of high-integration circuits.