Patents by Inventor YiSu Park

YiSu Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11367690
    Abstract: A semiconductor device has a substrate with a first opening and second opening formed in the substrate. A first semiconductor component is disposed on the substrate. The substrate is disposed on a carrier. A second semiconductor component is disposed on the carrier in the first opening of the substrate. A third semiconductor component is disposed in the second opening. The third semiconductor component is a semiconductor package in some embodiments. A first shielding layer may be formed over the semiconductor package. An encapsulant is deposited over the substrate, first semiconductor component, and second semiconductor component. A shielding layer may be formed over the encapsulant.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: June 21, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, Woonjae Beak, YiSu Park, OhHan Kim, HunTeak Lee, HeeSoo Lee
  • Publication number: 20200286835
    Abstract: A semiconductor device has a substrate with a first opening and second opening formed in the substrate. A first semiconductor component is disposed on the substrate. The substrate is disposed on a carrier. A second semiconductor component is disposed on the carrier in the first opening of the substrate. A third semiconductor component is disposed in the second opening. The third semiconductor component is a semiconductor package in some embodiments. A first shielding layer may be formed over the semiconductor package. An encapsulant is deposited over the substrate, first semiconductor component, and second semiconductor component. A shielding layer may be formed over the encapsulant.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, Woonjae Beak, YiSu Park, OhHan Kim, HunTeak Lee, HeeSoo Lee
  • Patent number: 10700011
    Abstract: A semiconductor device has a substrate with a first opening and second opening formed in the substrate. A first semiconductor component is disposed on the substrate. The substrate is disposed on a carrier. A second semiconductor component is disposed on the carrier in the first opening of the substrate. A third semiconductor component is disposed in the second opening. The third semiconductor component is a semiconductor package in some embodiments. A first shielding layer may be formed over the semiconductor package. An encapsulant is deposited over the substrate, first semiconductor component, and second semiconductor component. A shielding layer may be formed over the encapsulant.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 30, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, Woonjae Beak, YiSu Park, OhHan Kim, HunTeak Lee, HeeSoo Lee
  • Publication number: 20180158779
    Abstract: A semiconductor device has a substrate with a first opening and second opening formed in the substrate. A first semiconductor component is disposed on the substrate. The substrate is disposed on a carrier. A second semiconductor component is disposed on the carrier in the first opening of the substrate. A third semiconductor component is disposed in the second opening. The third semiconductor component is a semiconductor package in some embodiments. A first shielding layer may be formed over the semiconductor package. An encapsulant is deposited over the substrate, first semiconductor component, and second semiconductor component. A shielding layer may be formed over the encapsulant.
    Type: Application
    Filed: November 9, 2017
    Publication date: June 7, 2018
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: DeokKyung Yang, Woonjae Beak, YiSu Park, OhHan Kim, HunTeak Lee, HeeSoo Lee
  • Patent number: 9406579
    Abstract: A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor die with the heat spreader thermally connected to the substrate. A thermal interface material is formed over the semiconductor die. The underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. The channel extends partially through the insulating layer formed over the substrate with the insulating layer maintaining coverage over the substrate within a footprint of the channel.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: August 2, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DaeSik Choi, JoungIn Yang, Sang Mi Park, WonIl Kwon, YiSu Park
  • Patent number: 9390945
    Abstract: A semiconductor device has a substrate and insulating layer formed over a surface of the substrate. A first conductive layer is formed over the surface of the substrate. A second conductive layer is formed over an opposing surface of the substrate. A conductive via is formed through the substrate. An opening is formed in the insulating layer while leaving the first conductive layer intact. The opening narrows with a non-linear side or linear side. The opening can have a rectangular shape. A semiconductor die is mounted over the surface of the substrate. An underfill material is deposited between the semiconductor die and substrate. The opening in the insulating layer reduces a flow rate of the underfill material proximate to the opening. The flow rate of the underfill material proximate to the opening is substantially equal to a flow rate of the underfill material away from the opening.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: July 12, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: KyungHoon Lee, JoungIn Yang, Sang Mi Park, DaeSik Choi, YiSu Park
  • Patent number: 8723310
    Abstract: A method of manufacture of an integrated circuit packaging system includes providing a substrate; connecting an integrated circuit die; forming a molding having a temperature-dependent characteristic directly on the top surface of the substrate; and forming a coupling encapsulation having a coupled characteristic different from the temperature-dependent characteristic directly on the molding forms an encapsulation boundary between the coupling encapsulation and the molding.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 13, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: YiSu Park, KyungHoon Lee, Joungln Yang, SangMi Park, DaeSik Choi
  • Patent number: 8703535
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate; connecting an integrated circuit die to the package substrate with an internal interconnect; and forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: April 22, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: MinJung Kim, DaeSik Choi, MinWook Yu, YiSu Park
  • Publication number: 20130334714
    Abstract: A method of manufacture of an integrated circuit packaging system includes providing a substrate; connecting an integrated circuit die; forming a molding having a temperature-dependent characteristic directly on the top surface of the substrate; and forming a coupling encapsulation having a coupled characteristic different from the temperature-dependent characteristic directly on the molding forms an encapsulation boundary between the coupling encapsulation and the molding.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Inventors: YiSu Park, KyungHoon Lee, JoungIn Yang, SangMi Park, DaeSik Choi
  • Publication number: 20130328220
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming an integrated circuit device having a shaped side; mounting the integrated circuit device on the substrate; forming an encapsulation on the substrate and the integrate circuit device with the shaped side partially exposed from the encapsulation.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 12, 2013
    Inventors: KyungHoon Lee, JoungIn Yang, SangMi Park, YiSu Park, DaeSik Choi
  • Publication number: 20130328179
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate; connecting an integrated circuit die to the package substrate with an internal interconnect; and forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Inventors: MinJung Kim, DaeSik Choi, MinWook Yu, YiSu Park
  • Publication number: 20130299995
    Abstract: A semiconductor device has a substrate and insulating layer formed over a surface of the substrate. A first conductive layer is formed over the surface of the substrate. A second conductive layer is formed over an opposing surface of the substrate. A conductive via is formed through the substrate. An opening is formed in the insulating layer while leaving the first conductive layer intact. The opening narrows with a non-linear side or linear side. The opening can have a rectangular shape. A semiconductor die is mounted over the surface of the substrate. An underfill material is deposited between the semiconductor die and substrate. The opening in the insulating layer reduces a flow rate of the underfill material proximate to the opening. The flow rate of the underfill material proximate to the opening is substantially equal to a flow rate of the underfill material away from the opening.
    Type: Application
    Filed: May 8, 2012
    Publication date: November 14, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: KyungHoon Lee, JoungIn Yang, Sang Mi Park, DaeSik Choi, YiSu Park
  • Publication number: 20130300004
    Abstract: A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor die with the heat spreader thermally connected to the substrate. A thermal interface material is formed over the semiconductor die. The underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. The channel extends partially through the insulating layer formed over the substrate with the insulating layer maintaining coverage over the substrate within a footprint of the channel.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventors: DaeSik Choi, JoungIn Yang, Sang Mi Park, WonIl Kwon, YiSu Park