Abstract: A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.

Abstract: A semiconductor package comprises a lead frame, a die pad, bond pads, and leads. A die may be arranged on the die pad, the die comprising an integrated circuit. In an example, the die and at least a portion of the lead frame are encapsulated with a molding compound (MC). A first thickness of the MC over a first portion of the die is less than a second thickness over a second portion of the die to form a cavity in the MC and the MC directly contacts the first portion and the second portion of the die.

Abstract: According to a first aspect of the present invention there is provided a semiconductor device comprising: a die having a central active region, a top surface, a bottom surface, and sidewalls having a plurality of perforations therein, each perforation extending from a top end at the top surface to a bottom end at the bottom surface; a plurality of die pads on the top surface and extending from the central active region to respective top ends; a patterned back-side-metallization layer on the bottom surface, comprising a plurality of electrically isolated regions extending to respective bottom ends; metal coating partially filling the perforations and providing electrical connection between respective ones of the plurality of die pads and respective ones of the plurality of electrically isolated regions; and a passivation layer covering the top surface and the die pads.

Abstract: There is disclosed a packaged semiconductor device comprising: a leadframe having a first thickness; the leadframe comprising a die pad; a semiconductor die thereabove; and epoxy therebetween and arranged to bond the semiconductor die to the die pad; wherein in at least one region under the semiconductor die, the die pad has a second thickness less than the first thickness; wherein the die pad has at least one through-hole in the at least one region; and wherein the epoxy fills the at least one through-hole and extends thereunder and laterally beyond the through-hole. Corresponding leadframes, and an associated method of manufacture are also disclosed.

Abstract: Embodiments of a lead frame and packaged devices thereof, including a lead frame first and second rows of lead fingers respectively connected to first and second sides of the lead frame, the second side opposite the first side; a package body perimeter within which a package body of the packaged semiconductor device is formed; and a first die pad arm, wherein an end of the first die pad arm remains within the package body perimeter and is separated from the package body perimeter by a gap distance; wherein a first outermost lead finger of the first row of lead fingers is adjacent to the first die pad arm.

Abstract: Embodiments of a lead frame and packaged devices thereof, including a lead frame first and second rows of lead fingers respectively connected to first and second sides of the lead frame, the second side opposite the first side; a package body perimeter within which a package body of the packaged semiconductor device is formed; and a first die pad arm, wherein an end of the first die pad arm remains within the package body perimeter and is separated from the package body perimeter by a gap distance; wherein a first outermost lead finger of the first row of lead fingers is adjacent to the first die pad arm.

Abstract: A lead frame for a semiconductor device has a die pad for supporting a semiconductor die and intermediate lead fingers extending from a periphery of the package towards the die pad, and each having a bonding end near the die pad. Outer lead fingers are located adjacent respective tie bars edges, each outer lead finger extending from the periphery of the package towards the die pad. Each outer lead finger has a transverse region coupling two spaced longitudinal regions. The two spaced longitudinal regions each have a bonding region near the die pad. A semiconductor die is attached to the die pad and bond wires electrically couple connection pads of the semiconductor die to the bonding regions of each outer lead finger. Only one of the bond wires is bonded to the bonding region of the second longitudinal region.

Abstract: A wire capable of conducting electrical current has a polymer core and a coating layer surrounding the core. The coating layer, which may be, for example, gold or copper, conducts electrical current and the core provides strength so that the wire is able to withstand bending and breakage. Among other things, the polymer core wire is useful for connecting an integrated circuit to a lead frame or substrate.

Abstract: A system for dispensing an underfill material between an integrated circuit (IC) chip and a substrate includes a platform at which the underfill material is supplied. The IC chip and the substrate are mounted at the periphery of the platform. The platform rotates and facilitates the movement of the underfill material toward the IC chip and the substrate. The system further includes a Bernoulli tube that is located proximate to the IC chip and the substrate. The Bernoulli tube generates a low pressure in the proximity of the IC packages. The low pressure facilitates the dispensing of the underfill material between the IC chip and the substrate.

Abstract: A system for dispensing an underfill material between an integrated circuit (IC) chip and a substrate includes a platform at which the underfill material is supplied. The IC chip and the substrate are mounted at the periphery of the platform. The platform rotates and facilitates the movement of the underfill material toward the IC chip and the substrate. The system further includes a Bernoulli tube that is located proximate to the IC chip and the substrate. The Bernoulli tube generates a low pressure in the proximity of the IC packages. The low pressure facilitates the dispensing of the underfill material between the IC chip and the substrate.