Patents by Inventor Yi-Ting Lee
Yi-Ting Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250117524Abstract: This application discloses a computing system implementing a reliability verification tool to identify a portion of a layout design describing an integrated circuit includes a victim transistor having a gate connected to an aggressor transistor. The reliability verification tool can extract a resistance network for connections between the victim transistor and the aggressor transistor, and simulate the resistive network to determine connectivity between the wells of the victim transistor and the aggressor transistor occurs prior to the victim transistor having a gate connected to an aggressor transistor.Type: ApplicationFiled: June 16, 2022Publication date: April 10, 2025Applicant: Siemens Industry Software Inc.Inventors: Sridhar Srinivasan, Yi-Ting Lee, Lei Ling, Chung Lee
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Publication number: 20240090747Abstract: An endoscope device includes a head tube having a front opening and a lateral opening, a front image capturing lens disposed in the head tube and facing the front opening, an optical fiber disposed in the head tube and located at one side of the front image capturing lens, a lateral image capturing lens disposed in the head tube and facing the lateral opening, and a lateral light source disposed in the head tube and arranged adjacent to the lateral image capturing lens. As such, the endoscope device of present invention uses the optical fiber to transmit lights to the front image capturing lens and uses the lateral light source to provide lights to the lateral image capturing lens, such that the overall volume can be effectively reduced and a high intensity lighting effect can be achieved, thereby improving image capture resolution and image recognition accuracy.Type: ApplicationFiled: June 2, 2023Publication date: March 21, 2024Inventor: Yi-Ting LEE
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Patent number: 11901554Abstract: An anode material for a secondary battery is provided. The anode material for the secondary battery includes a metal oxide containing four or more than four elements, or an oxide mixture containing four or more than four elements. The metal oxide includes cobalt-copper-tin oxide, silicon-tin-iron oxide, copper-manganese-silicon oxide, tin-manganese-nickel oxide, manganese-copper-nickel oxide, or nickel-copper-tin oxide. The oxide mixture includes the oxide mixture containing cobalt, copper and tin, the oxide mixture containing silicon, tin and iron, the oxide mixture containing copper, manganese and silicon, the oxide mixture containing tin, manganese and nickel, the oxide mixture containing manganese, copper and nickel, or the oxide mixture containing nickel, copper and tin.Type: GrantFiled: June 15, 2022Date of Patent: February 13, 2024Assignee: National Tsing Hua UniversityInventors: Tri-Rung Yew, Kai-Wei Lan, Chun-Te Ho, Chia-Tung Kuo, Tien-Chi Ji, Yi-Ting Lee, Yun-Chen Tsai
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Patent number: 11894556Abstract: An anode material for a secondary battery is provided. The anode material for the secondary battery includes a metal oxide containing four or more than four elements, or an oxide mixture containing four or more than four elements. The metal oxide includes cobalt-copper-tin oxide, silicon-tin-iron oxide, copper-manganese-silicon oxide, tin-manganese-nickel oxide, manganese-copper-nickel oxide, or nickel-copper-tin oxide. The oxide mixture includes the oxide mixture containing cobalt, copper and tin, the oxide mixture containing silicon, tin and iron, the oxide mixture containing copper, manganese and silicon, the oxide mixture containing tin, manganese and nickel, the oxide mixture containing manganese, copper and nickel, or the oxide mixture containing nickel, copper and tin.Type: GrantFiled: April 30, 2020Date of Patent: February 6, 2024Assignee: National Tsing Hua UniversityInventors: Tri-Rung Yew, Kai-Wei Lan, Chun-Te Ho, Chia-Tung Kuo, Tien-Chi Ji, Yi-Ting Lee, Yun-Chen Tsai
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Publication number: 20230161148Abstract: An easy-to-assemble endoscope lens unit installed at a head tube of an insertion tube within an endoscope. The components of the endoscopic lens unit include a base having two extended holes, with each hole having an axis. The axes of the two extended holes being substantially parallel to one another, and each extended hole having an axis length that is greater than its radius length. The endoscopic lens unit further includes a camera lens, accommodated in one of the extended holes, with a front portion of the camera lens exposed at the base. Additionally, a projection lens is accommodated in the other extended hole, with the front portion of the projection lens also exposed at the base. The projection lens is used to project a projectile and display a predetermined pattern onto the projectile. An adhesive is applied to the base and at least one of the camera and projection lenses.Type: ApplicationFiled: September 6, 2022Publication date: May 25, 2023Inventor: Yi-Ting LEE
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Patent number: 11621521Abstract: A plug fixing structure is applied to fixing a power plug inserted into a power socket of an electronic device. The power plug has a plug portion and a main body portion. A first engaging structure is formed on an outer periphery of the power socket. The plug fixing structure includes a sleeve casing jacketing the main body portion to expose the plug portion and a first resilient arm having a first arm portion and a first front hook. The first arm portion protrudes from an outer surface of the sleeve casing. The first front hook extends from the first arm portion toward the first engaging structure. The first front hook is engaged with the first engaging structure when the plug portion is inserted into the power socket along a first axis, so as to constrain movement of the power plug along the first axis relative to the power socket.Type: GrantFiled: April 14, 2021Date of Patent: April 4, 2023Assignee: Qisda CorporationInventors: Cheng-Chih Huang, Yi-Ting Lee
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Publication number: 20220311000Abstract: An anode material for a secondary battery is provided. The anode material for the secondary battery includes a metal oxide containing four or more than four elements, or an oxide mixture containing four or more than four elements. The metal oxide includes cobalt-copper-tin oxide, silicon-tin-iron oxide, copper-manganese-silicon oxide, tin-manganese-nickel oxide, manganese-copper-nickel oxide, or nickel-copper-tin oxide. The oxide mixture includes the oxide mixture containing cobalt, copper and tin, the oxide mixture containing silicon, tin and iron, the oxide mixture containing copper, manganese and silicon, the oxide mixture containing tin, manganese and nickel, the oxide mixture containing manganese, copper and nickel, or the oxide mixture containing nickel, copper and tin.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Applicant: National Tsing Hua UniversityInventors: Tri-Rung Yew, Kai-Wei Lan, Chun-Te Ho, Chia-Tung Kuo, Tien-Chi Ji, Yi-Ting Lee, Yun-Chen Tsai
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Publication number: 20220190517Abstract: A plug fixing structure is applied to fixing a power plug inserted into a power socket of an electronic device. The power plug has a plug portion and a main body portion. A first engaging structure is formed on an outer periphery of the power socket. The plug fixing structure includes a sleeve casing jacketing the main body portion to expose the plug portion and a first resilient arm having a first arm portion and a first front hook. The first arm portion protrudes from an outer surface of the sleeve casing. The first front hook extends from the first arm portion toward the first engaging structure. The first front hook is engaged with the first engaging structure when the plug portion is inserted into the power socket along a first axis, so as to constrain movement of the power plug along the first axis relative to the power socket.Type: ApplicationFiled: April 14, 2021Publication date: June 16, 2022Inventors: Cheng-Chih Huang, Yi-Ting Lee
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Publication number: 20210226208Abstract: An anode material for a secondary battery is provided. The anode material for the secondary battery includes a metal oxide containing four or more than four elements, or an oxide mixture containing four or more than four elements. The metal oxide includes cobalt-copper-tin oxide, silicon-tin-iron oxide, copper-manganese-silicon oxide, tin-manganese-nickel oxide, manganese-copper-nickel oxide, or nickel-copper-tin oxide. The oxide mixture includes the oxide mixture containing cobalt, copper and tin, the oxide mixture containing silicon, tin and iron, the oxide mixture containing copper, manganese and silicon, the oxide mixture containing tin, manganese and nickel, the oxide mixture containing manganese, copper and nickel, or the oxide mixture containing nickel, copper and tin.Type: ApplicationFiled: April 30, 2020Publication date: July 22, 2021Applicant: National Tsing Hua UniversityInventors: Tri-Rung Yew, Kai-Wei Lan, Chun-Te Ho, Chia-Tung Kuo, Tien-Chi Ji, Yi-Ting Lee, Yun-Chen Tsai
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Patent number: 10985512Abstract: An electronic device includes a socket and a casing. The socket includes a first connecting structure and a second connecting structure. The casing includes a first side wall and a second side wall, wherein the first side wall is essentially perpendicular to the second side wall. The first side wall includes a third connecting structure and the second side wall includes a fourth connecting structure. The first connecting structure is connected to the third connecting structure along a first connecting axis and the second connecting structure is connected to the fourth connecting structure along a second connecting axis, such that the socket is fixed on the casing, wherein the first connecting axis is essentially perpendicular to the second connecting axis.Type: GrantFiled: December 16, 2019Date of Patent: April 20, 2021Assignee: Qisda CorporationInventors: Cheng-Chih Huang, Yi-Ting Lee
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Patent number: 10769340Abstract: Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.Type: GrantFiled: May 14, 2019Date of Patent: September 8, 2020Assignee: Mentor Graphics CorporationInventors: Sridhar Srinivasan, Yi-Ting Lee, Patrick D. Gibson, Padmaja Susarla, Alex Thompson
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Publication number: 20190354654Abstract: Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.Type: ApplicationFiled: May 14, 2019Publication date: November 21, 2019Inventors: Sridhar Srinivasan, Yi-Ting Lee, Patrick D. Gibson, Padmaja Susarla, Alex Thompson
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Publication number: 20190307908Abstract: The present disclosure features, a kit, including a first compartment including a volatile fluorinated compound dissolved in a C1-6 alcohol; and a second compartment including water. When the contents of the first and second compartments are mixed, spontaneous nucleation of nanodroplets of the volatile fluorinated compound can form in the aqueous phase to provide a dispersion of nanodroplets in the aqueous phase. The nanodroplets can be used to generate nanobubbles or microbubbles in ultrasound imaging.Type: ApplicationFiled: April 3, 2019Publication date: October 10, 2019Inventors: Lilo D. Pozzo, David Li, Yi-Ting Lee, Matthew O'Donnell
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Patent number: 9839344Abstract: A cannula assembly including a camera system to help provide multiple viewing angles of a surgical site. This added visualization provides the surgeon with more comprehensive feedback during the surgical procedure, leading to better patient outcome and a reduction in the surgical failure rate. The cannula has a main lumen and a smaller secondary lumen and is insertable into the surgical site for easy surgeon adaptation. The camera is coupled to the secondary lumen toward the side of the cannula. This allows the camera to provide visualization without obstructing the main lumen for the use of tools. The camera wiring runs through a long tube connected to the camera and through a handle at the end of the tube without blocking access to the surgical site.Type: GrantFiled: March 13, 2015Date of Patent: December 12, 2017Assignee: Arthroptics, L.L.C.Inventors: Jordan MacDonald, Christian Calyore, Yi-Ting Lee, Nandini Ravi, Adrienne Alimasa
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Patent number: 9785736Abstract: Aspects of the disclosed technology relate to techniques of connectivity-aware reduction of layout data. With various implementations of the disclosed technology, circuit elements of interest are selected in a circuit design which includes netlist information and layout data. Based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, nets of interest are determined. Cells of interest, comprising cells that are identified based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, are then determined. Based on the nets of interest and the cells of interest, layout geometric elements are selected and may be analyzed for design verification. For electrostatic discharge (ESD) protection verification, the cells of interest may further comprise cells that include portions of power supply grids on top metal layers.Type: GrantFiled: March 19, 2015Date of Patent: October 10, 2017Assignee: Mentor Graphics CorporationInventors: Yi-Ting Lee, Sridhar Srinivasan, Hung-Hsu Feng
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Publication number: 20170207344Abstract: A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.Type: ApplicationFiled: April 3, 2017Publication date: July 20, 2017Inventors: CHIEN-HAO WU, YI-TING LEE, HSIEN-TANG HU
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Patent number: 9673149Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and an invisible region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the visible region and the alignment mark is located in the invisible region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark.Type: GrantFiled: December 14, 2015Date of Patent: June 6, 2017Assignees: Hannstar Display (Nanjing) Corporation, Hannstar Display CorporationInventors: Chien-Hao Wu, Yi-Ting Lee
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Patent number: 9653488Abstract: A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.Type: GrantFiled: January 14, 2016Date of Patent: May 16, 2017Assignees: Hannstar Display (Nanjing) Corporation, Hannstar Display CorporationInventors: Chien-Hao Wu, Yi-Ting Lee, Hsien-Tang Hu
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Publication number: 20160204137Abstract: A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.Type: ApplicationFiled: January 14, 2016Publication date: July 14, 2016Inventors: CHIEN-HAO WU, YI-TING LEE, HSIEN-TANG HU
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Publication number: 20160204070Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and an invisible region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the visible region and the alignment mark is located in the invisible region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark.Type: ApplicationFiled: December 14, 2015Publication date: July 14, 2016Inventors: Chien-Hao WU, Yi-Ting LEE