Abstract: A cache unit that is configured to retain: a plurality of cache blocks; a plurality of owner indicators, and a plurality of validity marks. For each cache block of the plurality of cache blocks exists a corresponding owner indicator in the plurality of owner indicators. An owner indicator corresponding to a cache block is capable of identifying an entity that caused the cache block to be fetched to the cache unit. For each cache block of the plurality of cache blocks exists a corresponding validity mark in the plurality of validity marks. A validity mark corresponding to the cache block indicates whether a validation process performed on the cache block upon fetching thereof was successful. The cache unit may be useful for secure execution.

Abstract: A cache unit that is configured to retain: a plurality of cache blocks; a plurality of owner indicators, and a plurality of validity marks. For each cache block of the plurality of cache blocks exists a corresponding owner indicator in the plurality of owner indicators. An owner indicator corresponding to a cache block is capable of identifying an entity that caused the cache block to be fetched to the cache unit. For each cache block of the plurality of cache blocks exists a corresponding validity mark in the plurality of validity marks. A validity mark corresponding to the cache block indicates whether a validation process performed on the cache block upon fetching thereof was successful. The cache unit may be useful for secure execution.

Abstract: A method for writing data to a memory module, the method may include determining to write a representation of a data unit to a retired group of memory cells; searching for a selected retired group of memory cells that can store a representation of the data unit without being erased; and writing the representation of the data unit to the selected retired group of memory cells.

Abstract: A cache unit that is configured to retain: a plurality of cache blocks; a plurality of owner indicators, and a plurality of validity marks. For each cache block of the plurality of cache blocks exists a corresponding owner indicator in the plurality of owner indicators. An owner indicator corresponding to a cache block is capable of identifying an entity that caused the cache block to be fetched to the cache unit. For each cache block of the plurality of cache blocks exists a corresponding validity mark in the plurality of validity marks. A validity mark corresponding to the cache block indicates whether a validation process performed on the cache block upon fetching thereof was successful. The cache unit may be useful for secure execution.

Abstract: A method for writing data, the method may include evaluating current levels of multiple memory cells that belong to a certain set of memory cells or receiving an indication about the current levels of the multiple memory cells; encoding a new data unit to provide an encoded data unit to be written to the multiple memory cells while minimizing an amount of changes in levels of the maximum cell level among the multiple memory cells required for storing the encoded data unit; and writing the encoded data unit to the multiple memory cells.

Abstract: A system, computer readable medium and a method of operating a non volatile memory (NVM) array that comprises multiple NVM cells, the method comprises: receiving input data to be written to the non volatile memory; performing constraint coding on the input data to provide encoded data; wherein the constraint coding prevents the encoded data from comprising forbidden combinations of values; wherein the forbidden combinations of values are defined based on expected inter-cell coupling induced errors resulting from coupling between NVM cells; and writing the encoded data to the non volatile memory.

Abstract: A device, a computer readable medium and a method that may include performing a shortened read attempt of multiple data memory cells that store data to provide an estimate of the data; wherein the shortened read attempt has a duration that is shorter than a duration of a full read attempt; performing a shortened read attempt of redundant memory cells that store redundant information to provide an estimate of the redundant information; wherein the estimate of the redundant information is indicative of an expected number of data memory cells that store a certain logic value; determining, based on the estimate of the data, an estimated number of data memory cells that store the certain logic value; comparing the expected number to the estimated number; and providing the estimate of the data as a read result if the expected number and the estimated number equal each other.

Abstract: A method for writing data, the method may include evaluating current levels of multiple memory cells that belong to a certain set of memory cells or receiving an indication about the current levels of the multiple memory cells; encoding a new data unit to provide an encoded data unit to be written to the multiple memory cells while minimizing an amount of changes in levels of the maximum cell level among the multiple memory cells required for storing the encoded data unit; and writing the encoded data unit to the multiple memory cells.

Abstract: A method for writing data to a memory module, the method may include determining to write a representation of a data unit to a retired group of memory cells; searching for a selected retired group of memory cells that can store a representation of the data unit without being erased; and writing the representation of the data unit to the selected retired group of memory cells.

Abstract: A system, computer readable medium and a method of operating a non volatile memory (NVM) array that comprises multiple NVM cells, the method comprises: receiving input data to be written to the non volatile memory; performing constraint coding on the input data to provide encoded data; wherein the constraint coding prevents the encoded data from comprising forbidden combinations of values; wherein the forbidden combinations of values are defined based on expected inter-cell coupling induced errors resulting from coupling between NVM cells; and writing the encoded data to the non volatile memory.

Abstract: A device, a computer readable medium and a method that may include performing a shortened read attempt of multiple data memory cells that store data to provide an estimate of the data; wherein the shortened read attempt has a duration that is shorter than a duration of a full read attempt; performing a shortened read attempt of redundant memory cells that store redundant information to provide an estimate of the redundant information; wherein the estimate of the redundant information is indicative of an expected number of data memory cells that store a certain logic value; determining, based on the estimate of the data, an estimated number of data memory cells that store the certain logic value; comparing the expected number to the estimated number; and providing the estimate of the data as a read result if the expected number and the estimated number equal each other.

Abstract: A system and method for Near Video On Demand (NVOD) transmission of a program from a server to a plurality of clients. The program is partitioned into segments. Each segment is transmitted repeatedly, with the transmission rate of segments subsequent to the first segment being lower than the transmission rate of the first segment. The transmission of the segments is scheduled in a manner that minimizes the aggregate transmission bandwidth, subject to constraints related to client parameters such as client storage capacity and client recording rates. Preferably, the sequences are partitioned further into subsequences, and redundant subsequences are used for error correction. Preferably, the segments, or the subsegments, include metadata such as segment or subsegment length, segment or subsegment sequence number, or the time until the next transmission of the sequence or subsequence.

Abstract: A phased array antenna includes at least one digital modulator for phase shifting the signal of at least one antenna in the array. Each modulator includes a digital modulating element where the element can be a quadrature modulating element.

Abstract: An ambiguity resolver having an input for receiving a data string entered using an ambiguous keyboard, a comparator for comparing the data string to be searched against a plurality of prestored words to find at least one closest match to the data string, and an output for outputting a comparison result. An ambiguous keyboard is one in which more than one character is mapped to a single key, a particular example being a telephone keypad used for entering all the alphanumeric characters.

Abstract: A sewer system for storing and supplying data to a destination. The server system includes a plurality of disk drives for storing data, a buffer memory for temporarily storing a portion of the data from the disk drives which is soon to be supplied, a reconstruction unit for reconstructing a portion of the data from at least one of the disk drives using a portion of the data from a plurality of the remaining disk drives so that at least one of the disk drives holding data belonging to the current parity group can be bypassed (either because that disk is faulty or because there are already many queued read-requests for it), a control unit for controlling the server system, and an output unit for outputting data from either or both of the buffer memory and the reconstruction unit. The server system prevents congestion problems from persisting, reduces buffering requirements, and provides load balancing and fault tolerance.

Abstract: A track-pairing technique for use in recording and retrieving video data by alternating between a pair of tracks when recording and retrieving data segments of a data stream, a video server or recording disk is able to take advantage of zone bit recording when recording, yet data transfer rate upon retrieval is independent of track location. As a result, guaranteed throughput is substantially improved and the number of data streams which can be simultaneously sourced increases. The track-pairing technique can be embodied in a video server, a recording disk, a data layout method, or a data retrieval method.

Abstract: A system for the scheduled transmission of signals from source stations to destination stations in a passive, static, Single-Hop Interconnection (SHI) employing a plurality of Shared Directional Multichannels (SDMs) in a power-efficient and cost-effective manner. The system provides a practical implementation of any SHI built from a plurality of smaller SDMs whose salient feature is a significant degree of parallelism at low hardware cost while retaining the simplicity and reliability of a passive interconnection. The system is a scheme for wiring a SHI to retain the useful features of a SDM design for connecting (m) Source Stations each having (a) outputs to (n) Destination Stations each having one input such that, for m=n, the power split losses are reduced to a provably optimal value of (2n/a) and component count reduced to anlog.sub.2 (n/a), which is optimal for the optimal power split constraint.

Abstract: A rasterizer 10 for converting a datastream 12 which describes a page to be printed into a rasterized pagemap bitstream 13 to be sent to a printer. The rasterization is done in four stages using parallel processors in all stages except the first, and pipelining the processors between all of the stages. In the first stage 11, a scan processor 14 identifies and stores state-independent blocks 14 in the datastream. In the second stage 17, parallel block processors 22 convert the scanned blocks into stored intermediate-form data objects 20 and request preparation of often-used resources such as characters. In the third stage 23, the objects are sorted and stored by geographical region of the pagemap by parallel sort processors 24. In the fourth stage 31, the sorted objects are rasterized into pelmaps and placed in the pagemap by parallel bin processors 30. All four stages are pipelined.

Abstract: A shared directional multichannel for efficiently transmitting k=( log.sub.p n choose (p-1)) concurrent, non-interfering transmissions from a set of m.gtoreq.k source stations, each having p transmitters, to a set of n destination stations, each having one receiver, without active repeater components. The multichannel architecture permits implementation of an efficient single-hop multichannel system using optical star couplers in a manner that limits the power spreading loss to the n/p value known for bus-oriented networks instead of n.sup.2 /p. Several coupling stages are employed, each stage having a plurality of identical substantially-square directional couplers, to obtain channel concurrency k, which is an improvement over the concurrency p available in bus-oriented networks, without the higher power spreading loss normally arising from the larger number of connections between each source station and every destination station.

Abstract: A shared directional multichannel for efficiently transmitting k=( log.sub.p n choose (p-1) concurrent, non-interfering transmissions from a set of m.gtoreq.k source stations, each having p transmitters, to a set of n destination stations, each having one receiver, without active repeater components. The multichannel architecture permits implementation of an efficient single-hop multichannel system using optical star couplers in a manner that limits the power spreading loss to the n/p value known for bus-oriented networks instead of n.sup.2 /p. Several coupling stages are employed, each stage having a plurality of identical substantially-square directional couplers, to obtain channel concurrency k, which is an improvement over the concurrency p available in bus-oriented networks, without the higher power spreading loss normally arising from the larger number of connections between each source station and every destination station.