Abstract: A modular fail-safe memory and an address generation mechanism that provides load balancing when the memory is shared by a number of processors. A plurality of memory modules are used for the memory with no specific limit on the number of memory modules, and a checksum block is used to back-up corresponding blocks in the other memory modules. The checksum blocks are distributed across the memory modules, and an address generation mechanism determines the checksum location for a specific memory block. This address generation mechanism ensures that checksum blocks are equally divided between the memory modules so that there is no memory bottleneck, is easy to implement in hardware, and is extended to provide similar properties when a module failure occurs.

Abstract: At least two direct access storage devices (DASDs), which are predetermined to record the same data from a central processing unit (CPU), are normally kept synchronzied with each other except during the power up phase. The DASD synchronization is controlled and maintained by synchronization control means independent of any commands from the CPU. When one or more commands such as SEEK and SET SECTOR or LOCATE commands are transferred from the CPU to a control unit over a single data transfer path between them, desired identical records on the synchronized DASDs are concurrently located while the DASDs are disconnected from the data transfer path. Upon locating the desired identical records, the DASDs are reconnected to the data transfer path. Then, a WRITE command is transferred from the CPU to the control unit for concurrently recording the same data onto the synchronized DASDs at the desired record locations.

Abstract: A memory system backup for use in a tightly or loosely coupled multiprocessor system. A plurality of primary memory units having substantially the same configuration are backed up by a single memory unit of similiar configuration. The backup memory unit holds the checksum of all data held in all primary memory units. In the event of the failure of one of the primary memory units its contents can be recreated based on the data in the remaining non-failed memory unit and the checksum in the backup unit.

Abstract: In an apparatus for generating variable length codewords c(a.sub.i) and c(a.sub.j) responsive to corresponding fixed length codewords b(a.sub.i) and b(a.sub.j), where a.sub.i and a.sub.j are source alphabet characters, a.sub.i .epsilon. A.sub.1 and a.sub.j .epsilon. A.sub.2, ambiguity arises whenever any fixed length character to be encoded can instantaneously represent source characters a.sub.i and a.sub.j drawn from two or more dissimilar alphabets i.e. A.sub.1 or A.sub.2. This is resolved by the inclusion of a Markov processor in combination with the apparatus. The processor establishes the point in the sequence when transitions occur between fixed length characters in one alphabet to fixed length characters in another alphabet by the message context. The processor includes a map of state and transition paths.