Abstract: A peripheral bus switch that is adapted to connect together a pair of electrically independent peripheral buses to which arrays of peripheral devices (e.g. hard disk drives) are respectively connected in a peripheral bus interconnect system to ensure continuous access to all of the peripheral devices in the event that one of a pair of peripheral bus controllers which drive the peripheral buses should malfunction and require shutdown. The peripheral bus switch is a normally open switch that is connected between the pair of independent peripheral buses.

Abstract: A portable carrier for a disk drive including power control circuitry to enable a hot-plug connection between an external connector on the carrier and an opposing carrier mating connector on the back panel of an enclosure of a data storage system of the kind that is typically part of a file server, so that the disk drive can be powered from 5 and 12 volt power buses within the enclosure, but without damaging the disk drive or the opposing connectors at the moment of contact therebetween as a consequence of a current surge. The power control circuitry includes a timer and 5 volt and 12 volt carrier power switches (e.g., MOSFETs) that are respectively connected between the 5 volt and 12 volt power buses of the enclosure and the disk drive.

Abstract: A peripheral bus jumper block that establishes an external peripheral bridge for linking independent peripheral bus signal paths (i.e., sets of electrical traces formed on a peripheral bus panel) of a peripheral bus interconnect system so that the signal paths have the functional equivalent of a single, continuous peripheral bus path. Accordingly, arrays of computer peripherals (e.g. disk drives) that are coupled to the peripheral bus signal paths within a peripheral device enclosure are chained together so as to be capable of being operated by the same computer controller, whereby the peripheral bus interconnect system can be selectively reconfigured to improve system flexibility. The peripheral bus jumper block has a pair of peripheral bus connectors that are detachably connected to respective peripheral bus connectors from a pair of the peripheral bus signal paths that are to be linked together.

Abstract: A peripheral bus switch that is adapted to connect together a pair of electrically independent peripheral buses to which arrays of peripheral devices (e.g. hard disk drives) are respectively connected in a peripheral bus interconnect system to ensure continuous access to all of the peripheral devices in the event that one of a pair of peripheral bus controllers which drive the peripheral buses should malfunction and require shutdown. The peripheral bus switch is a normally open switch that is connected between the pair of independent peripheral buses.

Abstract: A data storage system having a plurality of computer peripheral equipment connected in electrical series with each other between a pair of peripheral host computers via peripheral cable segments. Each peripheral computer equipment includes a bank of data storage devices (e.g. disk drives) and a pair of signal repeaters. A first signal repeater is connected between bi-directional input and output peripheral cable connectors, and the second signal repeater is connected between the bank of data storage devices and each of the first repeater and the bi-directional output peripheral cable connector. By virtue of the foregoing, the data storage system of this invention is capable of enhanced reliability, flexibility and connectivity while effectively reducing signal delays, capacitive loading and transmission losses caused by transmission line effects, especially when the host computers and the computer peripheral equipment are positioned at distant locations relative to one another.

Abstract: System and method for controlling the transfer of data between a plurality of processors in a network. Synchronization between the processors is effected by means of asynchronously operated address counters which control the transmission of data from the processors. When a transmission occurs, the address counters are all set to a count corresponding to the address of the transmitting station, and in the event of a transmission from more than one processor, the address counters are reset to an initializing level. A station is permitted to transmit only when the count in its address counter corresponds to the address of the station.