Patents by Inventor Yi-Wei PENG

Yi-Wei PENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145691
    Abstract: The present invention is related to a novel positive electrode active material for lithium-ion battery. The positive electrode active material is expressed by the following formula: Li1.2NixMn0.8-x-yZnyO2, wherein x and y satisfy 0<x?0.8 and 0<y?0.1. In addition, the present invention provides a method of manufacturing the positive electrode active material. The present invention further provides a lithium-ion battery which uses said positive electrode active material.
    Type: Application
    Filed: March 14, 2023
    Publication date: May 2, 2024
    Inventors: CHUAN-PU LIU, YIN-WEI CHENG, SHIH-AN WANG, BO-LIANG PENG, CHUN-HUNG CHEN, JUN-HAN HUANG, YI-CHANG LI
  • Publication number: 20240096805
    Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Inventors: Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Patent number: 11923794
    Abstract: A motor control apparatus receives a DC power source through a DC terminal and is coupled to a motor. The motor control apparatus includes a brake, an inverter, and a controller. The brake is coupled to the inverter. The brake includes an energy-consuming component and a switch component. The controller controls the inverter to convert the DC power source to drive the motor. When the controller determines that the DC power source is interrupted, the controller stops controlling the inverter, and the switch component is self-driven turned on so that a back electromotive force generated by the motor is consumed through the energy-consuming component.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: March 5, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Te-Wei Wang, Yi-Kai Peng, Chen-Yeh Lee
  • Patent number: 9871137
    Abstract: The semiconductor device structures are provided. The semiconductor device structure includes a gate stack structure formed on a substrate and an isolation structure formed in the substrate. The semiconductor device structure further includes a source/drain stressor structure formed between the gate stack structure and the isolation structure and a metal silicide layer formed on the source/drain stressor structure. A portion of the metal silicide layer is below a top surface of the isolation structure.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Yeh Huang, Kai-Hsiang Chang, Chih-Chen Jiang, Yi-Wei Peng, Kuan-Yu Lin, Ming-Shan Tsai, Ching-Lun Lai
  • Publication number: 20170040451
    Abstract: The semiconductor device structures are provided. The semiconductor device structure includes a gate stack structure formed on a substrate and an isolation structure formed in the substrate. The semiconductor device structure further includes a source/drain stressor structure formed between the gate stack structure and the isolation structure and a metal silicide layer formed on the source/drain stressor structure. A portion of the metal silicide layer is below a top surface of the isolation structure.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 9, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO.,
    Inventors: Shin-Yeh HUANG, Kai-Hsiang CHANG, Chih-Chen JIANG, Yi-Wei PENG, Kuan-Yu LIN, Ming-Shan TSAI, Ching-Lun LAI
  • Patent number: 9478617
    Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Yeh Huang, Kai-Hsiang Chang, Chih-Chen Jiang, Yi-Wei Peng, Kuan-Yu Lin, Ming-Shan Tsai, Ching-Lun Lai
  • Publication number: 20160064486
    Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations.
    Type: Application
    Filed: October 29, 2015
    Publication date: March 3, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Yeh HUANG, Kai-Hsiang CHANG, Chih-Chen JIANG, Yi-Wei PENG, Kuan-Yu LIN, Ming-Shan TSAI, Ching-Lun LAI
  • Patent number: 9202916
    Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack structure. The semiconductor device structure further includes an isolation structure formed in the substrate and a source/drain stressor structure formed adjacent to the isolation structure. The source/drain stressor structure includes a capping layer which is formed along the (311) and (111) crystal orientations.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: December 1, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Yeh Huang, Kai-Hsiang Chang, Chih-Chen Jiang, Yi-Wei Peng, Kuan-Yu Lin, Ming-Shan Tsai, Ching-Lun Lai
  • Publication number: 20150187940
    Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack structure. The semiconductor device structure further includes an isolation structure formed in the substrate and a source/drain stressor structure formed adjacent to the isolation structure. The source/drain stressor structure includes a capping layer which is formed along the (311) and (111) crystal orientations.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Yeh HUANG, Kai-Hsiang CHANG, Chih-Chen JIANG, Yi-Wei PENG, Kuan-Yu LIN, Ming-Shan TSAI, Ching-Lun LAI