Abstract: A chip packaging apparatus and a preparation method thereof are provided, to modulate warpage of a chip, thereby resolving a problem of mismatch between a warpage degree of the chip and a warpage degree of a substrate. The chip packaging apparatus includes a chip, a substrate, and a warpage modulation structure, where a surface that is of the chip and that faces the substrate is electrically connected to the substrate, the warpage modulation structure is disposed on a surface that is of the chip and that is opposite to the substrate, and a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip.

Abstract: A chip is mounted on a surface of the substrate, and the thermally conductive cover is disposed on a side that is of the chip and that is away from the substrate. There is a filling area on a surface that is of the thermally conductive cover and that faces the substrate, and the filling area is opposite to the chip. There is an accommodation cavity whose opening faces the substrate in the filling area. A thermal interface material layer is filled between the chip and a bottom surface of the accommodation cavity. Between an opening edge of the accommodation cavity and the substrate, there is a first gap connected to the accommodation cavity. The filling material encircles a side surface of the thermal interface material layer, so that the filling material separates the side surface of the thermal interface material layer from air.

Abstract: A packaged IC includes a fanout layer, a processor having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the processor, and a memory coupled to a second surface of the RDL, wherein a first portion of the memory is disposed outside of a footprint of the processor and a second portion of the memory is disposed within the footprint of the processor. The packaged IC further includes first conductive posts disposed beneath the first portion of the memory proximate a first side of the processor for providing communication links between the processor and memory, and second conductive posts coupled between the fanout layer and conductive features of the RDL coupled to power inputs of the second portion of the memory, the second conductive posts proximate a second side of the processor.

Abstract: A chip packaging apparatus and a preparation method thereof are provided, to modulate warpage of a chip, thereby resolving a problem of mismatch between a warpage degree of the chip and a warpage degree of a substrate. The chip packaging apparatus includes a chip, a substrate, and a warpage modulation structure, where a surface that is of the chip and that faces the substrate is electrically connected to the substrate, the warpage modulation structure is disposed on a surface that is of the chip and that is opposite to the substrate, and a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip.