Abstract: A method for joining a semiconductor integrated circuit (IC) chip in a flip chip configuration, via pillar bump, to solderable metal contact pads, leads or circuit lines on the ciruitized surface of a chip carrier, as well as the resulting chip package, are disclosed. The semiconductor device is attached to the substrate via no flow underfill under thermal compression bonding. Integration of this structure and assembly method enables to incorporate low coefficient of thermal expansion (CTE) no flow underfill and achieve high assembly yield, especially for lead free bumps. The present invention provides a solution for a flip chip package with fine pitch, high pin count and lead free requirements.

Abstract: A method for joining a semiconductor integrated circuit (IC) chip in a flip chip configuration, via pillar bump, to solderable metal contact pads, leads or circuit lines on the ciruitized surface of a chip carrier, as well as the resulting chip package, are disclosed. The semiconductor device is attached to the substrate via no flow underfill under thermal compression bonding. Integration of this structure and assembly method enables to incorporate low coefficient of thermal expansion (CTE) no flow underfill and achieve high assembly yield, especially for lead free bumps. The present invention provides a solution for a flip chip package with fine pitch, high pin count and lead free requirements.