Patents by Inventor Yiyi Ma

Yiyi Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10658238
    Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: May 19, 2020
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
  • Publication number: 20180040514
    Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.
    Type: Application
    Filed: October 16, 2017
    Publication date: February 8, 2018
    Inventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
  • Patent number: 9824924
    Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: November 21, 2017
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
  • Patent number: 9679870
    Abstract: An integrated circuit (IC) device includes an IC and encapsulating material surrounding the IC. Leads are coupled to the IC and extend outwardly from sides of the encapsulating material, with each lead having three contiguous exposed segments with upper and lower bends defining a Z-shape. In another example, the leads include an upper horizontal segment, lower horizontal segment, and intermediate curved segment extending upwardly from the upper horizontal segment and downwardly to the lower horizontal segment.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: June 13, 2017
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang, Wei Zhen Goh
  • Patent number: 9576912
    Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor substrate, a back end of line (BEOL) layer on the semiconductor substrate and having a peripheral edge recessed inwardly from an adjacent peripheral edge of the semiconductor substrate. A first dielectric layer is over the BEOL layer and wraps around the peripheral edge of the BEOL layer. A redistribution layer is over the first dielectric layer and a second dielectric layer is over the redistribution layer.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: February 21, 2017
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang
  • Publication number: 20160293512
    Abstract: An electronic device may include a substrate, an active IC die above the substrate, and a dummy IC die above the active IC die. The electronic device may include a first adhesive layer between the active IC die and the dummy IC die, and a heat sink layer above the dummy IC die and extending laterally outwardly to define a gap between the substrate and opposing portions of the heat sink layer.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 6, 2016
    Inventors: Yiyi MA, Kim-Yong GOH, Xueren ZHANG
  • Publication number: 20160190029
    Abstract: A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections on a lower surface thereof and coupling respective bond pads of the IC die to the grid array with bond wires. The method may also include forming a first encapsulating layer over the IC die and bond wires and positioning a heat spreader on the substrate above the first encapsulating layer after forming the first encapsulating layer. The method may further include forming a second encapsulating layer over the first encapsulating layer and embedding the heat spreader in the second encapsulating layer.
    Type: Application
    Filed: December 30, 2014
    Publication date: June 30, 2016
    Inventors: Kim-Yong GOH, Yiyi Ma, Xueren Zhang
  • Patent number: 9379034
    Abstract: A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections on a lower surface thereof and coupling respective bond pads of the IC die to the grid array with bond wires. The method may also include forming a first encapsulating layer over the IC die and bond wires and positioning a heat spreader on the substrate above the first encapsulating layer after forming the first encapsulating layer. The method may further include forming a second encapsulating layer over the first encapsulating layer and embedding the heat spreader in the second encapsulating layer.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 28, 2016
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Kim-Yong Goh, Yiyi Ma, Xueren Zhang
  • Publication number: 20160172262
    Abstract: An integrated circuit (IC) device includes an IC and encapsulating material surrounding the IC. Leads are coupled to the IC and extend outwardly from sides of the encapsulating material, with each lead having three contiguous exposed segments with upper and lower bends defining a Z-shape. In another example, the leads include an upper horizontal segment, lower horizontal segment, and intermediate curved segment extending upwardly from the upper horizontal segment and downwardly to the lower horizontal segment.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Inventors: Yiyi MA, Kim-Yong GOH, Xueren ZHANG, Wei Zhen GOH
  • Publication number: 20150084171
    Abstract: A non-lead (QFN) semiconductor package is disclosed. The package includes a die attach pad and a semiconductor die supported by the die attached pad. The semiconductor die includes a plurality of pads on an active surface thereof. The package further includes a plurality of terminal leads, an encapsulant that encapsulates the semiconductor die, and a redistribution layer including a plurality of interconnections electrically connecting the pads to the terminal leads. A method of making the package is also disclosed.
    Type: Application
    Filed: September 23, 2013
    Publication date: March 26, 2015
    Applicant: STMicroelectronics Pte. Ltd.
    Inventors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang
  • Patent number: 8907465
    Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Kim-Yong Goh, Yiyi Ma, Wei Zhen Goh
  • Publication number: 20140291782
    Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: STMicroelectronics Pte Ltd.
    Inventors: Kim-Yong Goh, Yiyi Ma, Wei Zhen Goh
  • Publication number: 20140291812
    Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: STMicroelectronics Pte Ltd.
    Inventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
  • Patent number: 8497587
    Abstract: A thermally enhanced expanded wafer level ball grid array package. The expanded wafer level ball grid array package includes an integrated thermally conductive heat dissipater. In one embodiment the heat dissipater is positioned in close proximity to a non-active face of a die and is separated from the non-active face by a thermal interface material. In another embodiment the heat dissipater includes legs that displace the heat dissipater a short distance from the non-active die face, with the intervening space occupied by encapsulation material. In yet another embodiment, the thermal interface material exists between the non-active die face and the heat dissipater, but extends beyond the edge of the semiconductor die to also cover a portion of the encapsulation material. Methods for making the various embodiments of the expanded wafer level ball grid array package are also shown.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 30, 2013
    Assignee: STMicroelectronics Pte Ltd.
    Inventor: Yiyi Ma
  • Publication number: 20130093072
    Abstract: A leadframe includes a die pad and a protective wall surrounding the die pad. A semiconductor die is situated on the die pad. Indentations are formed on the four inner corners of the protective wall adjacent the corners of the semiconductor die.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 18, 2013
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventors: Xueren Zhang, Wingshenq Wong, Kim-Yong Goh, Yiyi Ma
  • Publication number: 20130001740
    Abstract: A heat spreader is provided for use with a thermally enhanced flip-chip ball grid array package. In the package, a semiconductor die is positioned front-side down on a package substrate, coupled thereto via solder balls. Passive devices can also be coupled to the substrate alongside the die. The heat spreader is positioned over the substrate and die, in thermal contact with the die. A projection in the center of the heat spreader makes contact with the back surface of the die via a thermal interface material, to draw heat from the die for improved cooling. The projection enables close contact with a thinned die while accommodating thicker passive devices positioned around the die on the substrate.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventor: Yiyi Ma
  • Publication number: 20110156236
    Abstract: A thermally enhanced expanded wafer level ball grid array package. The expanded wafer level ball grid array package includes an integrated thermally conductive heat dissipater. In one embodiment the heat dissipater is positioned in close proximity to a non-active face of a die and is separated from the non-active face by a thermal interface material. In another embodiment the heat dissipater includes legs that displace the heat dissipater a short distance from the non-active die face, with the intervening space occupied by encapsulation material. In yet another embodiment, the thermal interface material exists between the non-active die face and the heat dissipater, but extends beyond the edge of the semiconductor die to also cover a portion of the encapsulation material. Methods for making the various embodiments of the expanded wafer level ball grid array package are also shown.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: STMICROELECTRONICS ASIA PACIFIC PTE LTD.
    Inventor: Yiyi Ma
  • Patent number: 6528166
    Abstract: Nickel composite particles having a layer of a nickel-containing spinel on at least a part of the surface of nickel particles, or nickel composite particles having an oxide layer of metals other than nickel on at least a part of the surface of nickel particles and a layer of a nickel-containing spinel at an interface between the nickel particles and the metal oxide layer. The nickel composite particles are produced by forming fine liquid droplets from a solution containing (a) at least one thermally decomposable nickel compound and (b) at least one thermally decomposable metal compound capable of forming a spinel together with nickel; and heating the liquid droplets at a temperature higher than the decomposition temperatures of the compound (a) and (b) to nickel particles and simultaneously deposit a nickel-containing spinel layer, or further a metal oxide layer on the spinel layer.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: March 4, 2003
    Assignee: Shoei Chemical Inc.
    Inventors: Yuji Akimoto, Kazuro Nagashima, Hiroshi Yoshida, Yiyi Ma
  • Publication number: 20020114950
    Abstract: Nickel composite particles having a layer of a nickel-containing spinel on at least a part of the surface of nickel particles, or nickel composite particles having an oxide layer of metals other than nickel on at least a part of the surface of nickel particles and a layer of a nickel-containing spinel at an interface between the nickel particles and the metal oxide layer. The nickel composite particles are produced by forming fine liquid droplets from a solution containing (a) at least one thermally decomposable nickel compound and (b) at least one thermally decomposable metal compound capable of forming a spinel together with nickel; and heating the liquid droplets at a temperature higher than the decomposition temperatures of the compound (a) and (b) to nickel particles and simultaneously deposit a nickel-containing spinel layer, or further a metal oxide layer on the spinel layer.
    Type: Application
    Filed: November 15, 2001
    Publication date: August 22, 2002
    Applicant: SHOEI CHEMICAL INC.
    Inventors: Yuji Akimoto, Kazuro Nagashima, Hiroshi Yoshida, Yiyi Ma
  • Patent number: 6403218
    Abstract: Nickel composite particles having a layer of a nickel-containing spinel on at least a part of the surface of nickel particles, or nickel composite particles having an oxide layer of a metal other than nickel on at least a part of the surface of nickel particles and a layer of a nickel-containing spinel at an interface between the nickel particles and the metal oxide layer. The nickel composite particles are produced by forming fine liquid droplets from a solution containing (a) at least one thermally decomposable nickel compound and (b) at least one thermally decomposable metal compound capable of forming a spinel together with nickel; and heating the liquid droplets at a temperature higher than the decomposition temperatures of compounds (a) and (b) to form nickel particles and simultaneously deposit a nickel-containing spinel layer, or further, a metal oxide layer on the spinel layer.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: June 11, 2002
    Assignee: Shoei Chemical Inc.
    Inventors: Yuji Akimoto, Kazuro Nagashima, Hiroshi Yoshida, Yiyi Ma