Abstract: A high-density programmable logic device is presented, comprising two or more logic built-in blocks interconnected by a programmable global interconnect multiplex matrix. Each logic built-in block contains four groups of four macrocells and four I/O cells, two sub AND arrays and four sub OR arrays. Each sub OR array couples a group of macrocells, and each sub AND array drives two sub OR arrays. The sub AND and OR arrays can either function independently or be connected together by AND array or OR array connection facilities, to extend the logic capability. Every macrocell can be flexibly controlled by three levels of control signal: global, logic built-in block wide or separate. The outputs from the macrocells and the inputs from I/O cells can be fed locally back through the local feedback path, and also fed globally to other logic built-in blocks, through the global interconnect multiplex matrix.

Abstract: A programmable logic device (PLD) includes logic built-in blocks (LBB) connected with a programmable interconnection array (PIA). Each LBB has two configurable logic cells sharing a group of control product terms, which serve as global and local control signals. Each configurable logic cell employs a programmable array (an AND gate array connected to two OR gate arrays), followed by two groups of Multi-Register Macro Cells (MRMC). The multi-register macro cells contain registers, which are grouped into logic control cells, multiplexers and I/O cells. The registers receive sum terms from the OR gate arrays as inputs, while the multiplexers direct the flow of the outputs and feedbacks, which can be either latched outputs from registers or direct sum terms from the OR gate arrays. All of the controls of the multi-register macro cells in an LBB are available from shared control product terms, thus providing both local and global control signals.

Abstract: A structure and method for high density programmable logic device (PLD) testing, programming, and verification is disclosed. The device employs non-volatile memory cells, such as electrically erasable programmable ROM (EEPROM), as its programmable elements. The structure and method allow the PLD to work in the normal operation state and also in a number of utility states. In normal operation state, the PLD performs the configured logic function as programmed by the user. In utility states, the PLD can be programmed, verified and tested. A state machine and a decoder are used to perform these procedures. They include bit program (write), verify (read), bulk program (write all), bulk erase (erase all), checker board and inverse checker board program, cell current test, address decode test, softwrite test and logical function test data preload. All the utilities are in a serial algorithm and are controlled by an internal state machine, which needs as few as four dedicated pins to interface with the PLD proper.