Abstract: A bispecific antibody simultaneously targeting two different epitopes or targets is coupled with a camptothecin drug to form a bispecific antibody-toxin conjugate that is stable in treatment and excellent in uniformity, and a drug-to-antibody ratio (DAR) thereof is 6.0-8.0. The antibody-toxin conjugate has a structure as represented by general formula (I), wherein Ab represents the bispecific antibody simultaneously targeting two different epitopes or targets, which is coupled with a linker-camptothecin drug. In addition, the present invention further relates to a preparation and purification method for the antibody-toxin conjugate, and an application thereof in tumor treatment. Furthermore, the present invention further relates to a linker-drug compound capable of being coupled with Ab to form the antibody-toxin conjugate.

Abstract: A bispecific antibody simultaneously targeting two different epitopes or targets is coupled with a camptothecin drug to form a bispecific antibody-toxin conjugate that is stable in treatment and excellent in uniformity, and a drug-to-antibody ratio (DAR) thereof is 6.0-8.0. The antibody-toxin conjugate has a structure as represented by general formula (I), wherein Ab represents the bispecific antibody simultaneously targeting two different epitopes or targets, which is coupled with a linker-camptothecin drug. In addition, the present invention further relates to a preparation and purification method for the antibody-toxin conjugate, and an application thereof in tumor treatment. Furthermore, the present invention further relates to a linker-drug compound capable of being coupled with Ab to form the antibody-toxin conjugate.

Abstract: A blockchain-based AI model training method is provided, comprising: building an original AI model according to features of data sets; randomly allocating participants in a training process proportionally into three categories: a model trainer, a model verifier and a model uploader, prior to start of each round of training of the original AI model; during each round of training, generating, by the model trainer and the model verifier, respective partial models of a current round; checking, by the model verifier, partial models generated by the model trainer through using partial models generated locally; aggregating, by the model uploader, all partial models passing the checking of the model verifier to obtain a global model of the current round, and packing the global model, checking results and all the partial models of the current round into a blockchain.

Abstract: A camptothecin drug having a highly stable hydrophilic connecting unit and its conjugate, or its pharmaceutically acceptable salt thereof, including methods for preparation thereof, and its applications in preventing and/or treating cancer. The conjugate can specifically bind to receptors highly expressed in tumor cells. The conjugates have excellent water solubility, stability, and homogeneity, and can be used for preventing and/or treating tumors and/or other diseases.

Abstract: A method to build a persistent memory (PM)-based data storage system without involving a processor (CPU) at storage nodes is disclosed which includes storing data in one or more storage nodes that only include PM and no CPUs, with data stored in PM in form of link lists, accessing data stored in the one or more storage nodes' PM directly by remote compute nodes through a network, maintaining metadata associated with the data by one or more global controllers (metadata servers), upon request by a user to read or write data, the compute nodes contacting the one or more metadata servers to obtain location of data of interest in form of pointers (shortcuts), and the compute nodes sending network requests directly to the one or more storage nodes' PM to locate latest version of data by tracing the link list from the associated shortcut to corresponding tails.

Abstract: An antitumor pharmaceutical camptothecin derivative and an antibody-drug conjugate thereof. By means of a series of molecular structure modifications, an optimal camptothecin antitumor drug is obtained, so as to be more suitable as a drug for antibody conjugation.

Abstract: A method to build a persistent memory (PM)-based data storage system without involving a processor (CPU) at storage nodes is disclosed which includes storing data in one or more storage nodes that only include PM and no CPUs, with data stored in PM in form of link lists, accessing data stored in the one or more storage nodes' PM directly by remote compute nodes through a network, maintaining metadata associated with the data by one or more global controllers (metadata servers), upon request by a user to read or write data, the compute nodes contacting the one or more metadata servers to obtain location of data of interest in form of pointers (shortcuts), and the compute nodes sending network requests directly to the one or more storage nodes' PM to locate latest version of data by tracing the link list from the associated shortcut to corresponding tails.

Abstract: A method for manufacturing a semiconductor device may include the following steps: providing a spacer structure on a first side of a stack structure, wherein the stack structure includes a mask and a conductor; providing an etch stop layer, wherein a portion of the etch stop layer directly contacts both the mask and a portion of the spacer structure; providing a dielectric material member on the etch stop layer; partially removing the first dielectric material member to expose the portion of the etch stop layer; removing the portion of the etch stop layer to expose the portion of the spacer structure; removing the portion of the spacer structure to expose a side of the mask and to form a first spacer; and providing a second spacer, which directly contacts both the first spacer and the side of the mask.

Abstract: A method for fabricating an NAND flash memory includes providing a semiconductor substrate with a core region and a peripheral region, forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a first dielectric layer. The method further includes forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, and forming a solid dielectric layer through a solidification treatment process performed on the flowable dielectric layer. Voids and seams formed in the top portion of the first dielectric layer are filled by the solid dielectric layer. The method also includes removing the solid dielectric layer and a portion of the first dielectric layer to expose a top portion of the gate stack structures, and forming a metal silicide layer on each gate stack structure.

Abstract: A method for manufacturing a semiconductor device may include the following steps: providing a spacer structure on a first side of a stack structure, wherein the stack structure includes a mask and a conductor; providing an etch stop layer, wherein a portion of the etch stop layer directly contacts both the mask and a portion of the spacer structure; providing a dielectric material member on the etch stop layer; partially removing the first dielectric material member to expose the portion of the etch stop layer; removing the portion of the etch stop layer to expose the portion of the spacer structure; removing the portion of the spacer structure to expose a side of the mask and to form a first spacer; and providing a second spacer, which directly contacts both the first spacer and the side of the mask.

Abstract: A method for fabricating an NAND flash memory includes providing a semiconductor substrate with a core region and a peripheral region, forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a first dielectric layer. The method further includes forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, and forming a solid dielectric layer through a solidification treatment process performed on the flowable dielectric layer. Voids and seams formed in the top portion of the first dielectric layer are filled by the solid dielectric layer. The method also includes removing the solid dielectric layer and a portion of the first dielectric layer to expose a top portion of the gate stack structures, and forming a metal silicide layer on each gate stack structure.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a gate having a first material on a substrate and a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. A characteristic of a portion of the substrate between adjacent sidewall spacers is changed using the layer of second material and the sidewall spacers as a mask. An isotropic wet etch process is performed to remove the substrate portion with a changed characteristic to form a recess in the substrate. An orientation selective wet etching process is performed on the recess to shape the inner walls of the recess into sigma-shape. Changing a substrate characteristic in conjunction with isotropic wet etching prevents the substrate from being damaged, and therefore can obtain defect free epitaxial SiGe growth performance.

Abstract: Described herein is a system and method for an efficient cache warm-up. The system and method may copy data blocks from a primary storage device to a cache memory device. The system and method may identify a subset of data blocks stored on the primary storage device as candidate data blocks for copying to the cache memory device during a cache warm-up period. A cost effectiveness for copying the candidate data blocks to the cache memory device may be determined. In some embodiments, the cost effectiveness may be calculated based on one or more latency values associated with the primary storage device and the cache memory device. The candidate data blocks may be copied to the cache memory device based on the cost effectiveness.

Abstract: This invention discloses a reaction apparatus for wafer treatment, an electrostatic chuck and a wafer temperature control method, in the field of semiconductor processing. The electrostatic chuck comprises an insulating layer for supporting a wafer and a lamp array disposed in the insulating layer. Each lamp of the lamp array can be independently controlled to turn on and off and/or to adjust the output power. By controlling the on/off switch and/or output power of each lamp of the lamp array the temperature of the wafer held on the ESC is adjusted and temperature non-uniformity can be more favorably adjusted, greatly improving wafer temperature uniformity, particularly alleviating non-radial temperature non-uniformity.

Abstract: This disclosure relates to a method of forming a gate pattern and a semiconductor device. The gate pattern comprises a plurality of parallel gate bars, and each gate bar is broken up by gaps. The method comprises: making an etching characteristic of a gate material layer at least at positions where the gaps are to be formed different from that at remaining positions; forming a plurality of parallel openings in a second resist layer; performing a first etching process on the gate material layer with the second resist layer as a mask, wherein portions of the gate material layer at least at the positions where the gaps are to be formed are selectively left; and performing a second etching process on the gate material layer so as to selectively remove the portions. This method can more accurately control the shape and size of the gate pattern.

Abstract: This disclosure is directed to a method of forming a gate pattern and a semiconductor device. The method comprises: providing a plurality of stacked structures which are parallel to each other and extend continuously in a first direction, and which are composed of a gate material bar and an etching barrier bar thereon; leaving second resist regions between gaps to be formed adjacent to each other across gate bars by a second photolithography process; selectively removing the etching barrier bars by a second etching process; forming a third resist layer having a plurality of openings parallel to each other and extending continuously in a second direction substantially perpendicular to the first direction by a third photolithography process; and forming the gate pattern by a third etching process. The method is capable of having a larger photolithography process window and better controlling the shape and size of a gate pattern.

Abstract: A method for forming a metal gate includes providing a substrate, subsequently forming a dummy gate on the substrate, forming spacers on sidewalls of the dummy gate, forming a stop layer on the substrate, the dummy gate and spacers of the dummy gate, and forming a sacrificial dielectric layer on the dummy gate and the stop layer. The method further includes removing a part of the sacrificial dielectric layer and the stop layer until the dummy gate is exposed and, removing a residual sacrificial dielectric layer, depositing an interlayer dielectric layer on the dummy gate and the stop layer, polishing the interlayer dielectric layer until the dummy gate is exposed, removing the dummy gate to form a trench, and forming a metal gate in the trench. The interlayer dielectric layer is flat and substantially flush with the dummy gate, so that no recesses are formed thereon.

Abstract: A duplicate-aware disk array (DADA) leaves duplicated content on the disk array largely unmodified, instead of removing duplicated content, and then uses these duplicates to improve system performance, reliability, and availability of the disk array. Several implementations disclosed herein are directed to the selection of one duplicate from among a plurality of duplicates to act as the proxy for the other duplicates found in the disk array. Certain implementations disclosed herein are directed to scrubbing latent sector errors (LSEs) on duplicate-aware disk arrays. Other implementations are directed to disk reconstruction/recovery on duplicate-aware disk arrays. Yet other implementations are directed to load balancing on duplicate-aware disk arrays.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The method comprises: providing a substrate with a first dielectric layer and a gate, wherein the gate is embedded in the first dielectric layer and an upper portion of the gate is an exposed first metal; and covering only the exposed first metal with a conductive material that is harder to be oxidized than the first metal by a selective deposition. An advantage of the present invention is that the metal of the upper surface of the gate is prevented from being oxidized by covering the metal gate with the conductive material that is relatively harder to be oxidized, thereby facilitating the formation of an effective electrical connection to the gate.

Abstract: A method of fabricating semiconductor device includes forming a plurality of gates on a substrate, forming a top layer on a top surface of each gate, forming sidewall spacers on opposite sides of each gate, and forming sacrificial spacers on the sidewall spacers. The method further includes performing a dry etching process on the substrate using the top layer and the sacrificial spacers as a mask to form a recess of a first width in the substrate between two adjacent gates, performing an isotropic wet etching process on the recess to expand the first width to a second width, and performing an orientation selective wet etching process on the recess to shape the rectangular-shaped recess into a ?-shaped recess.