Abstract: An integrated circuit die (10) includes a substrate (64), a plurality of metal interconnect layers (62) formed over the substrate (64), an insulating layer (58), a first pad (12), a second pad (14), and a probe pad (16). The first pad (12) is formed over the insulating layer (58) at an edge (11) of the integrated circuit die (10). The second pad (14) is formed over the insulating layer (58) adjacent to the first pad (12) on a side of the first pad (12) that is opposite to the edge (11). The probe pad (16) is formed over the insulating layer (58) on a side of the second pad (14) that is opposite to the edge (11), wherein the probe pad (16) is electrically connected to the first pad (12). The probe pad (16) may be formed over active circuitry of the substrate instead of over a peripheral area of the die (10), thus reducing the surface area of the die (10).