Patents by Inventor Yo-Hao Tu

Yo-Hao Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10819322
    Abstract: An apparatus is provided that includes a frequency doubler circuit and a duty cycle adjusting circuit. The frequency doubler circuit includes a multiplexer, a variable delay circuit and a divide-by-2 circuit. The multiplexer selects one of a first and a second clock signals having opposite phases according to a selection signal to generate a frequency doubled clock signal. The variable delay circuit delays the frequency doubled clock signal. The divide-by-2 circuit divides a frequency of the frequency doubled clock signal to generate the selection signal. The duty cycle adjusting circuit includes an average voltage generation circuit and a comparison circuit. The average voltage generation circuit generates an average voltage value of the frequency doubled clock signal. The comparison circuit generates a control signal according to a comparison result of the average voltage value and a reference voltage to control the duty cycle of the frequency doubled clock signal.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: October 27, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: An-Ming Lee, Chia-Liang Lin, Yo-Hao Tu, Yu-Hsiang Chen
  • Publication number: 20200235725
    Abstract: An apparatus is provided that includes a frequency doubler circuit and a duty cycle adjusting circuit. The frequency doubler circuit includes a multiplexer, a variable delay circuit and a divide-by-2 circuit. The multiplexer selects one of a first and a second clock signals having opposite phases according to a selection signal to generate a frequency doubled clock signal. The variable delay circuit delays the frequency doubled clock signal. The divide-by-2 circuit divides a frequency of the frequency doubled clock signal to generate the selection signal. The duty cycle adjusting circuit includes an average voltage generation circuit and a comparison circuit. The average voltage generation circuit generates an average voltage value of the frequency doubled clock signal. The comparison circuit generates a control signal according to a comparison result of the average voltage value and a reference voltage to control the duty cycle of the frequency doubled clock signal.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 23, 2020
    Inventors: An-Ming LEE, Chia-Liang LIN, Yo-Hao TU, Yu-Hsiang CHEN
  • Patent number: 9024693
    Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Jen-Chieh Liu, Chi-Yang Chang, Yo-Hao Tu, Kuo-Hsing Cheng
  • Publication number: 20140361840
    Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.
    Type: Application
    Filed: September 13, 2013
    Publication date: December 11, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Jen-Chieh Liu, Chi-Yang Chang, Yo-Hao Tu, Kuo-Hsing Cheng