Abstract: A semiconductor memory device has a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel.

Abstract: A semiconductor memory device has a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel.

Abstract: The present invention provide a method for forming a triple well. The triple well includes an n-well, a first p-well surrounded with the n-well and a second p-well apart from the first p-well and adjacent to the n-well. According to the present invention, only one conductivity type of impurities are implanted in each well. Therefore, it is possible to prevent the decrease of the carrier mobility and increase of the leakage current.

Abstract: A semiconductor device having an adjacent P-well and N-well, such as a complementary metal oxide semiconductor (CMOS) transistor, on a silicon on insulator (SOI) substrate has a latch-up problem caused by the parasitic bipolar effect. This invention provides a semiconductor device removing the latch-up problem and methods for fabricating the same. A semiconductor device according to the present invention has a T-shaped field oxide layer connected to a buried oxide layer of the SOI substrate to prevent the latch-up problem.

Abstract: A method for fabricating an SOI wafer, which involves bonding a plurality of wafers each provided at its upper surface with an oxide film in such a manner that the oxide film of each wafer is upwardly disposed, heating the resulting wafer structure to form an ingot, and cutting the ingot into pieces which will be used as SOI wafers. Accordingly, it is possible to achieve an improvement in productivity in the fabrication of SOI wafers. As a result, mass production can be achieved. The invention also provides a method for fabricating an SOI device, which involves forming a silicon film having a desired thickness beneath a field oxide film and implanting impurity ions in the silicon film, thereby forming doped regions. Accordingly, it is possible to solve the problem caused by floating of the semiconductor substrate.

Abstract: A semiconductor memory device has a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel.

Abstract: The present invention relates to a transistor for providing protection from electrostatic discharge when a semiconductor device is exposed to electrostatic state, the transistor for providing protection from Electrostatic Discharge(ESD) being characterized by the fact that in case the gate length of a transistor is L, the gate length at the edges of the transistor is longer than the gate length L, and that the gate length is fixed as L and the edge of the transistor, in which the gate is adjacent to the active regions, has a grooved shape with an acute angle, and also the present invention makes the high-intensity electric field alleviated, and also enables the current to flow uniformly over the overall gate, and the heating effect is prevented, resulting in a prolonged life expectancy of the device.

Abstract: A method for fabricating a metal oxide silicon field effect transistor (MOSFET) wherein a polysilicon layer is deposited over a gate oxide film serving to insulate the gate of the MOSFET from the substrate of the MOSFET. The polysilicon layer serves to prevent the gate oxide film from being etched upon forming a gate electrode using a metal film or metal silicide side walls as a mask. Accordingly, it is possible to prevent a short circuit from occurring between the semiconductor substrate and gate electrode of the MOSFET upon forming the gate electrode.

Abstract: A semiconductor device having a silicon-on-insulator structure, and a method for fabricating the semiconductor device, wherein a thick silicon oxide film is formed on each side wall of an active silicon substrate, thereby obtaining an increased threshold voltage at the edge of the active silicon substrate. The semiconductor device includes a first silicon substrate, a first silicon oxide film formed over the first silicon substrate, a second silicon substrate on the first silicon oxide film, second silicon oxide films, respectively disposed on opposite side walls of the second silicon substrate, a gate oxide film formed on the second silicon substrate, a gate electrode formed over the gate oxide film, and source/drain impurity diffusion regions, respectively formed in portions of the second silicon substrate disposed at both sides of the gate electrode.

Abstract: A sense amplifier comprising a data refresh amplifier for supplying voltages to true and complementary bit lines in response to a first control signal to amplify true and complementary data on the true and complementary bit lines, respectively, a first transistor for amplifying current of the true data on the true bit line in response to a second control signal and transferring the amplified true data to a true input/output line, a second transistor for amplifying current of the complementary data on the complementary bit line in response to the second control signal and transferring the amplified complementary data to a complementary input/output line, a first switch for selectively forming a current path between the true input/output line and the true bit line, and a second switch for selectively forming a current path between the complementary input/output line and the complementary bit line.

Abstract: A fully planarized concave transistor is produced having a structure, wherein a lightly doped drain(LDD) region and a source/drain region are formed and accumulated on a semiconductor substrate in a predetermined pattern, a thick insulating layer is formed on the surface and the sidewall of the source/drain, a gate formed between the source and drain, with a gate insulating layer is formed between the source and the gate, and between the drain and the gate to insulate therebetween.

Abstract: A method for forming contact holes in a semiconductor device, involving formation of a ring-shaped pad at a contact region. The ring-shaped pad is used as an etch barrier film upon forming a contact hole. The use of such a ring-shaped pad enables easy formation of a contact hole with a critical dimension. In accordance with this method, it is possible to increase a process margin upon the formation of contact holes for providing contacts with a critical dimension while maintaining an insulation between neighboring conductors.

Abstract: A sense amplifier comprising a data refresh amplifier for supplying voltages to true and complementary bit lines in response to a first control signal to amplify true and complementary data on the true and complementary bit lines, respectively, a first transistor fox amplifying current of the true data on the true bit line in response to a second control signal and transferring the amplified true data to a true input/output line, a second transistor for amplifying current of the complementary data on the complementary bit line in response to the second control signal and transferring the amplified complementary data to a complementary input/output line, a first switch for selectively forming a current path between the true input/output line and the true bit line, and a second switch for selectively forming a current path between the complementary input/output line and the complementary bit line.

Abstract: A method of manufacturing a semiconductor device, capable of securing an alignment margin between bit lines and a storage node contact is disclosed herein.

Abstract: When contacting a bit line and a charge storage electrode to a source/drain of the MOS transistor during a manufacturing process of a highly integrated semiconductor device, a contact pad is formed by filling up polysilicon into a contact hole that had been made using a self-align method in order not to damage the word line or the bit line as a result of a small processing margin during a contact hole forming process. Also, the occurrence of a topological difference during a semiconductor manufacturing process is minimized by forming an oxide layer such as SOG, BPSG, TEOS, and PECVD oxide over the top of the field oxide for a flattening effect.