Patents by Inventor Yo Ichikawa

Yo Ichikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7244972
    Abstract: In a field effect transistor, an Si layer 11, an SiC (Si1?yCy) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: July 17, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Kubo, Yo Ichikawa, Akira Asai, Takahiro Kawashima
  • Patent number: 6844227
    Abstract: In a field effect transistor, an Si layer, an SiC (Si1-yCy) channel layer, a CN gate insulating film made of a carbon nitride layer (CN) and a gate electrode are deposited in this order on an Si substrate. The thickness of the SiC channel layer is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region and a drain region are formed on opposite sides of the SiC channel layer, and a source electrode and a drain electrode are provided on the source region and the drain region, respectively.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: January 18, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Kubo, Yo Ichikawa, Akira Asai, Takahiro Kawashima
  • Publication number: 20040227169
    Abstract: In a field effect transistor, an Si layer 11, an SiC (Si1-yCy) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.
    Type: Application
    Filed: June 17, 2004
    Publication date: November 18, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Kubo, Yo Ichikawa, Akira Asai, Takahiro Kawashima
  • Patent number: 6713790
    Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: March 30, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Asai, Teruhito Oonishi, Takeshi Takagi, Tohru Saitoh, Yoshihiro Hara, Koichiro Yuki, Katsuya Nozawa, Yoshihiko Kanzawa, Koji Katayama, Yo Ichikawa
  • Publication number: 20030102490
    Abstract: In a field effect transistor, an Si layer 11, an SiC (Si1-yCy) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.
    Type: Application
    Filed: August 15, 2002
    Publication date: June 5, 2003
    Inventors: Minoru Kubo, Yo Ichikawa, Akira Asai, Takahiro Kawashima
  • Publication number: 20020197809
    Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.
    Type: Application
    Filed: August 7, 2002
    Publication date: December 26, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Akira Asai, Teruhito Oonishi, Takeshi Takagi, Tohru Saitoh, Yoshihiro Hara, Koichiro Yuki, Katsuya Nozawa, Yoshihiko Kanzawa, Koji Katayama, Yo Ichikawa
  • Patent number: 6455364
    Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: September 24, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Asai, Teruhito Oonishi, Takeshi Takagi, Tohru Saitoh, Yoshihiro Hara, Koichiro Yuki, Katsuya Nozawa, Yoshihiko Kanzawa, Koji Katayama, Yo Ichikawa
  • Patent number: 6399993
    Abstract: In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: June 4, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Teruhito Ohnishi, Akira Asai, Takeshi Takagi, Tohru Saitoh, Yo Ichikawa, Yoshihiro Hara, Koichiro Yuki, Katsuya Nozawa, Koji Katayama, Yoshihiko Kanzawa
  • Patent number: 5996199
    Abstract: A surface acoustic module is stable, and its operation frequencies can be varied with high precision. A method of manufacturing the surface acoustic module prevents the module's electrodes from being broken during separation of a sheet of modules into individual components. The surface acoustic module includes electrodes for transmitting and receiving a surface acoustic wave, a surface acoustic wave transmitting substrate, a high resistance thin film, and a thin film for differentiating the transmission velocity of a surface acoustic wave at the high resistance thin film from that at the substrate. The method includes the steps of forming a metallic film on a sheet of the surface acoustic wave transmitting substrate, of forming the electrodes on the metallic film, and of irradiating light or the like to the metallic film so as to increase the film's resistivity.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: December 7, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yo Ichikawa, Hideaki Adachi, Kentaro Setsune, Syunichiro Kawashima
  • Patent number: 5828079
    Abstract: A field-effect type superconducting device includes a channel layer. The channel layer includes Bi-based oxide compound containing Cu. A source electrode contacts the channel layer. A drain electrode contacts the channel layer. A gate insulating film made of insulating material extends on on the channel layer. A gate electrode extends on the gate insulating film.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: October 27, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Mizuno, Hideaki Adachi, Yo Ichikawa, Kentaro Setsune
  • Patent number: 5815900
    Abstract: A surface acoustic module is stable, and its operation frequencies can be varied with high precision. A method of manufacturing the surface acoustic module prevents the module's electrodes from being broken during separation of a sheet of modules into individual components. The surface acoustic module includes electrodes for transmitting and receiving a surface acoustic wave, a surface acoustic wave transmitting substrate, a high resistance thin film, and a thin film for differentiating the transmission velocity of a surface acoustic wave at the high resistance thin film from that at the substrate. The method includes the steps of forming a metallic film on a sheet of the surface acoustic wave transmitting substrate, of forming the electrodes on the metallic film, and of irradiating light or the like to the metallic film so as to increase the film's resistivity.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: October 6, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yo Ichikawa, Hideaki Adachi, Kentaro Setsune, Syunichiro Kawashima
  • Patent number: 5757250
    Abstract: A surface acoustic module is stable, and its operation frequencies can be varied with high precision. A method of manufacturing the surface acoustic module prevents the module's electrodes from being broken during separation of a sheet of modules into individual components. The surface acoustic module includes electrodes for transmitting and receiving a surface acoustic wave, a surface acoustic wave transmitting substrate, a high resistance thin film, and a thin film for differentiating the transmission velocity of a surface acoustic wave at the high resistance thin film from that at the substrate. The method includes the steps of forming a metallic film on a sheet of the surface acoustic wave transmitting substrate, of forming the electrodes on the metallic film, and of irradiating light or the like to the metallic film so as to increase the film's resistivity.
    Type: Grant
    Filed: February 11, 1997
    Date of Patent: May 26, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yo Ichikawa, Hideaki Adachi, Kentaro Setsune, Syunichiro Kawashima
  • Patent number: 5731270
    Abstract: An oxide is formed which will form an oxide superconductor containing a Cu-O atomic layer. The oxide is hydrogenated. The oxide is oxidized after it is hydrogenated. The hydrogenation and the oxidization are executed simultaneously with or after the oxide is formed. The hydrogenation and the oxidization improve the superconducting characteristics of the oxide superconductor.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: March 24, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kentaro Setsune, Yo Ichikawa, Akira Enokihara, Masahiro Sakai
  • Patent number: 5434126
    Abstract: A thin-film superconductor includes a substrate, a ferroelectric film, and a superconducting oxide film. The ferroelectric film extends on the substrate. The ferroelectric film is made of a crystal contains Bi and O. The superconducting oxide film extends on the ferroelectric film, and containing Bi, Cu, and an alkaline-earth metal element. The superconducting oxide film may contain at least two different alkaline-earth metal elements.
    Type: Grant
    Filed: March 25, 1994
    Date of Patent: July 18, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yo Ichikawa, Koichi Mizuno, Toshifumi Sato, Hideaki Adachi, Kentaro Setsune