Abstract: An image processing device includes a high-speed bus and a peripheral bus linked via a bus bridge, and connected to the buses are a CPU for carrying out computations and control of image processing, a data transceiving FIFO memory for carrying out transceiving of image compression data with a host device, a frame memory for storing image expansion data from an electronic camera and the like and displaying the data on a display panel, and a compression/expansion circuit for carrying out compression of image expansion data and expansion of image compression data. The CPU and the frame memory are connected to the high-speed bus and the data transceiving FIFO memory is connected to the peripheral bus. The arrangement of the image processing device makes the CPU operate more efficiently to achieve overall increased speed in image processing.

Abstract: A test circuit employs hardware to test a memory cell in a memory block. The address of an error cell detected is stored in a first or second error address register. Access made by a processor to the address of the error cell would be detected by a first or second address comparator. Data is then written to a first or second correction register, which serves as an alternative cell, or data is read from one of the registers.

Abstract: A display section A and a body section B including a CPU and serving to carry out a signal processing are connected to each other through a folding section C. The display section of a folding portable apparatus is provided with a display panel 2, a camera 3 and image processing means 27 for receiving photographed image data from the camera, carrying out an image processing and directly supplying display image data to the display section. In the case in which data including the image data are to be supplied from the body section to the display section or from the display section to the body section, a data transmitting/receiving function between the CPU and the image processing means is enabled.

Abstract: A test circuit employs hardware to test a memory cell in a memory block. The address of an error cell detected is stored in a first or second error address register. Access made by a processor to the address of the error cell would be detected by a first or second address comparator. Data is then written to a first or second correction register, which serves as an alternative cell, or data is read from one of the registers.

Abstract: A display section A and a body section B including a CPU and serving to carry out a signal processing are connected to each other through a folding section C. The display section of a folding portable apparatus is provided with a display panel 2, a camera 3 and image processing means 27 for receiving photographed image data from the camera, carrying out an image processing and directly supplying display image data to the display section. In the case in which data including the image data are to be supplied from the body section to the display section or from the display section to the body section, a data transmitting/receiving function between the CPU and the image processing means is enabled.

Abstract: A motor control circuit generates a signal representing a rotation frequency of a motor. It produces a motor speed error signal based on the rotation frequency. The error signal is changed by a speed gain circuit and supplied to the motor driving circuit through a filter. The filter is for preventing an oscillation in a servo loop. When the motor speed is out of a predetermined range, a gain of the speed error signal is reduced and the filter is disabled.

Abstract: A circuit for controlling a rotating member is provided with an input capture register which reads out the value of a free running counter at a timing of an FG (frequency generated) pulse generated in accordance with a rotation of a rotating member. A central processing unit performs an interrupt operation based on a PG (phase generated) pulse generated in accordance with a rotation of the rotating member and an interrupt operation based on the FG pulse. A pulse width modulation circuit rotates the rotating member by use of a speed error signal and a phase error signal which are obtained by the interrupt operations of the central processing unit. A rotating member driver is also provided. The central processing unit calculates the phase error signal from an output of the input capture register based on an FG pulse generated after the generation of the PG pulse.

Abstract: A circuit which supplies a clock pulse to activate the microcomputer includes a sinusoidal wave oscillation circuit. A sinusoidal waveulse converting circuit is provided which converts an oscillation output of the sinusoidal wave oscillation circuit into a clock pulse when the level of the oscillation output exceeds a predetermined value. The clock pulse is supplied to the microcomputer by the converting circuit. The converting circuit includes a first inverter having a threshold value on the high voltage side of the central level of the amplitude of the oscillation output and a second inverter having a threshold value on the low voltage side of the central level of the amplitude. In addition, the converting circuit includes an RS flip flop which generates a clock pulse whose level changes alternately by the outputs of the first and second inverters.

Abstract: A MOSFET whose back gate area is independent of a substrate is employed as a level-slicing transistor which is simultaneously used for alternately turning ON and turning OFF four analog switches in accordance with the relation between the voltages of the output terminal and inverted input voltage of the output terminal is limited to V.sub.B .+-.V.sub.th, where V.sub.th is the amplitude at the threshold level of the levelslicing transistor and V.sub.B is the bias voltage.