Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa).

Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa). When the mask body satisfies these inequalities, the generation of recesses during ultrasonic cleaning of the mask can be suppressed.

Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa). When the mask body satisifies these inequalities, the generation of recesses during ultrasonic cleaning of the mask can be suppressed.

Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa).

Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa).

Abstract: A deposition mask includes a mask body and a through-hole provided in the mask body and through which a deposition material passes when the deposition material is deposited on a deposition target substrate. The mask body satisfies y?950 and y?23x?1280 when an indentation elastic modulus is x (GPa) and a 0.2% yield strength is y (MPa).

Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.

Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.

Abstract: A circuit member includes a lead frame material having a die pad, a lead part to be electrically connected with a semiconductor chip, and an outer frame configured to support the die pad and the lead part. The lead frame material includes a resin sealing region. Roughened faces 10A to 10C and 11A to 11C, each having an average roughness Ra of 0.3 ?m or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer formed by laminating a Ni plated layer and a Pd plated layer in this order or a three-layer plated layer formed by laminating the Ni plated layer, the Pd plated layer and an Au plated layer in this order is formed on the whole surface of the lead frame material.

Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.

Abstract: A circuit member 20 includes a lead frame material 1 having a die pad 3, a lead part 6 to be electrically connected with a semiconductor chip 30, and an outer frame 2 configured to support the die pad and the lead part. The lead frame material includes a resin sealing region 9. Roughened faces 10A to 10C and 11A to 11C, each having an average roughness Ra of 0.3 ?m or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer 12A formed by laminating a Ni plated layer 13 and a Pd plated layer 14 in this order or a three-layer plated layer 12B formed by laminating the Ni plated layer 13, the Pd plated layer 14 and an Au plated layer 15 in this order is formed on the whole surface of the lead frame material.

Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.

Abstract: A member for mounting of semiconductor is comprised of a substrate, a concave portions for electrode and a concave portion for wire formed on one surface of the substrate, electrode terminals formed in the concave portions for electrode, and a wire formed in the concave portion for wire, in which the concave portions for electrode terminals are formed deeper than the concave portions for wire. In the pattern-forming process, resist pattern having an opening for wire and openings for electrode in which a width of the openings for electrode is larger than a width of the portion for wire is formed on one surface of a substrate. In the etching process, a substrate is half-cut by etching a substrate through the resist pattern as a mask so that concave portions for electrode and a opening for wire are formed on the surface of the substrate.

Abstract: A member for mounting of semiconductor is comprised of a substrate, a concave portions for electrode and a concave portion for wire formed on one surface of the substrate, electrode terminals formed in the concave portions for electrode, and a wire formed in the concave portion for wire, in which the concave portions for electrode terminals are formed deeper than the concave portions for wire. In the pattern-forming process, resist pattern having an opening for wire and openings for electrode in which a width of the openings for electrode is larger than a width of the portion for wire is formed on one surface of a substrate. In the etching process, a substrate is half-cut by etching a substrate through the resist pattern as a mask so that concave portions for electrode and a opening for wire are formed on the surface of the substrate.