Patents by Inventor Yo Takeda
Yo Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7667249Abstract: A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.Type: GrantFiled: October 24, 2007Date of Patent: February 23, 2010Assignee: Seiko Epson CorporationInventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
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Patent number: 7612396Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.Type: GrantFiled: June 26, 2007Date of Patent: November 3, 2009Assignee: Seiko Epson CorporationInventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
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Patent number: 7508019Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.Type: GrantFiled: June 26, 2007Date of Patent: March 24, 2009Assignee: Seiko Epson CorporationInventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
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Patent number: 7482647Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.Type: GrantFiled: June 26, 2007Date of Patent: January 27, 2009Assignee: Seiko Epson CorporationInventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
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Patent number: 7473962Abstract: A semiconductor device includes: a semiconductor layer; a first area and a second area which are demarcated by a separation insulating layer provided on the semiconductor layer; a nonvolatile memory provided on the first area; a plurality of MOS transistors provided on the second area; a first interlayer insulating layer embedded between the plurality of MOS transistors on the second area; and a second interlayer insulating layer provided above the first area and the second area. The second interlayer insulating layer is provided as if covering the nonvolatile memory on the first area and, on the second area, provided, being above the first interlayer insulating layer, as if covering the MOS transistor.Type: GrantFiled: January 12, 2006Date of Patent: January 6, 2009Assignee: Seiko Epson CorporationInventors: Yutaka Maruo, Susumu Inoue, Yo Takeda
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Publication number: 20080067564Abstract: A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.Type: ApplicationFiled: October 24, 2007Publication date: March 20, 2008Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
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Patent number: 7304337Abstract: A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.Type: GrantFiled: November 28, 2005Date of Patent: December 4, 2007Assignee: Seiko Epson CorporationInventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
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Publication number: 20070246760Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.Type: ApplicationFiled: June 26, 2007Publication date: October 25, 2007Applicant: SEIKO EPSON CORPORATIONInventors: Susumu INOUE, Yo TAKEDA, Yutaka MARUO
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Publication number: 20070246759Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.Type: ApplicationFiled: June 26, 2007Publication date: October 25, 2007Applicant: SEIKO EPSON CORPORATIONInventors: Susumu INOUE, Yo TAKEDA, Yutaka MARUO
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Publication number: 20070246758Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.Type: ApplicationFiled: June 26, 2007Publication date: October 25, 2007Applicant: SEIKO EPSON CORPORATIONInventors: Susumu INOUE, Yo TAKEDA, Yutaka MARUO
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Patent number: 7253462Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.Type: GrantFiled: October 13, 2005Date of Patent: August 7, 2007Assignee: Seiko Epson CorporationInventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
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Patent number: 7126175Abstract: A semiconductor device comprising: a first light shielded region including a first semiconductor element, the first light shielded region being defined by a first light shielding wall provided in the periphery thereof; a second light shielded region including a second semiconductor element, the second light shielded region being defined by a second light shielding wall provided in the periphery thereof and being provided in a position adjacent to the first light shielded region; a first opening provided in the first light shielding wall; a second opening provided in the second light shielding wall and positioned facing to the first opening; a first wiring layer coupled with the first semiconductor element and brought out to the outside of the first light shielded region from the first opening; a second wiring layer coupled with the second semiconductor element and brought out to the outside of the second light shielded region from the second opening; and a light shielding film provided at least above a regionType: GrantFiled: November 29, 2005Date of Patent: October 24, 2006Assignee: Seiko Epson CorporationInventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
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Publication number: 20060170030Abstract: A semiconductor device includes: a semiconductor layer; a first area and a second area which are demarcated by a separation insulating layer provided on the semiconductor layer; a nonvolatile memory provided on the first area; a plurality of MOS transistors provided on the second area; a first interlayer insulating layer embedded between the plurality of MOS transistors on the second area; and a second interlayer insulating layer provided above the first area and the second area. The second interlayer insulating layer is provided as if covering the nonvolatile memory on the first area and, on the second area, provided, being above the first interlayer insulating layer, as if covering the MOS transistor.Type: ApplicationFiled: January 12, 2006Publication date: August 3, 2006Inventors: Yutaka Maruo, Susumu Inoue, Yo Takeda
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Publication number: 20060138496Abstract: A semiconductor device comprising: a first light shielded region including a first semiconductor element, the first light shielded region being defined by a first light shielding wall provided in the periphery thereof; a second light shielded region including a second semiconductor element, the second light shielded region being defined by a second light shielding wall provided in the periphery thereof and being provided in a position adjacent to the first light shielded region; a first opening provided in the first light shielding wall; a second opening provided in the second light shielding wall and positioned facing to the first opening; a first wiring layer coupled with the first semiconductor element and brought out to the outside of the first light shielded region from the first opening; a second wiring layer coupled with the second semiconductor element and brought out to the outside of the second light shielded region from the second opening; and a light shielding film provided at least above a regionType: ApplicationFiled: November 29, 2005Publication date: June 29, 2006Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
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Publication number: 20060131623Abstract: A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.Type: ApplicationFiled: November 28, 2005Publication date: June 22, 2006Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
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Publication number: 20060131626Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.Type: ApplicationFiled: October 13, 2005Publication date: June 22, 2006Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo