Patents by Inventor Yoad Lustig

Yoad Lustig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Satisfiability (SAT) based bounded model checkers
    Patent number: 8489380
    Abstract: Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Daniel Geist, Mark Ginzburg, Yoad Lustig, Ishai Rabinovotz, Ohad Shacham, Rachel Tzoref
  • Satisfiability (SAT) based bounded model checkers
    Patent number: 8108195
    Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Daniel Geist, Mark Ginzburg, Yoad Lustig, Ishai Rabinovitz, Ohad Shacham, Rachel Tzoref
  • Satisfiability (SAT) Based Bounded Model Checkers
    Publication number: 20110213605
    Abstract: Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains.
    Type: Application
    Filed: May 16, 2011
    Publication date: September 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: Daniel Geist, Mark Ginzburg, Yoad Lustig, Ishai Rabinovotz, Ohad Shacham, Rachel Tzoref
  • SATISFIABILITY (SAT) BASED BOUNDED MODEL CHECKERS
    Publication number: 20100324881
    Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.
    Type: Application
    Filed: August 10, 2010
    Publication date: December 23, 2010
    Inventors: Daniel Geist, Mark Ginzburg, Yoad Lustig, Ishai Rabinovitz, Ohad Shacham, Rachel Tzoref
  • Satisfiability (SAT) based bounded model checkers
    Patent number: 7835898
    Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Daniel Geist, Mark Ginzburg, Yoad Lustig, Ishai Rabinovitz, Ohad Shacham, Rachel Tzoref
  • Satisfiability (SAT) based bounded model checkers
    Publication number: 20070118340
    Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.
    Type: Application
    Filed: November 22, 2005
    Publication date: May 24, 2007
    Applicant: International Business Machines Corporation
    Inventors: Daniel Geist, Mark Ginzburg, Yoad Lustig, Ishai Rabinovitz, Ohad Shacham, Rachel Tzoref