Abstract: A system and a method are provided for implementing a power-saving sleep mode in a synchronous circuit core having multiple clock domains including primary and secondary clock domains. The primary clock domain has states of awake, asleep, doze, and waking. The doze and waking states are transient states between the awake and asleep states. One or more secondary clock domains each have states of secondary awake and secondary asleep. The doze and waking states are used to eliminate race conditions between the primary and secondary clock domains. If the core has two or more secondary clock domains, the secondary clock domains each have an additional state of sleep-pending. The sleep-pending state is a transient state between the secondary awake and secondary asleep states. One or more synchronization logics are coupled between the primary and secondary clock domains.

Abstract: Speech Label Accelerators (SLAs) are provided that comprise an indirect memory, atom value memory, and adder circuitry. Optionally, the SLAs also comprise an accumulator, a load/accumulate multiplexer (mux), and a control unit. There are a variety of different configurations for the adder circuitry, and a configuration can be selected based on speed, power, and area requirements. A number of techniques are provided that allow a system having an SLA to handle more dimensions, atoms, or both than the SLA was originally designed for. A “zig-zag” method is provided that speeds processing in a system when using more dimensions than the SLA was originally designed for. Generally, the kernels used by the SLA will be Gaussian and separable, but non-Gaussian kernels and partially separable kernels may also be used by the SLA.

Abstract: The invention presents a method for selecting test cases in a test simulation of logic designs to improve speed and effectiveness of such testing. The method for selecting such test cases after such test cases are generated includes generating a test-coverage file and a harvest-goals file for the test case. The harvest-goals file contains a list of events and initial goal for each event. Harvest criteria is used to determined whether the number of hits for each event meets the initial goal. By applying the harvest criteria to the test case, it is determined whether to harvest the test case. The test case is saved and identified for harvest, if the test case is determined to be harvested. Also, the harvest-goals file is adjusted, if the test case is determined to be harvested.

Abstract: A system and a method are provided for implementing a power-saving sleep mode in a synchronous circuit core having multiple clock domains including primary and secondary clock domains. The primary clock domain has states of awake, asleep, doze, and waking. The doze and waking states are transient states between the awake and asleep states. One or more secondary clock domains each have states of secondary awake and secondary asleep. The doze and waking states are used to eliminate race conditions between the primary and secondary clock domains. If the core has two or more secondary clock domains, the secondary clock domains each have an additional state of sleep-pending. The sleep-pending state is a transient state between the secondary awake and secondary asleep states. One or more synchronization logics are coupled between the primary and secondary clock domains.

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node, with a node controller, that are coupled to a node interconnect. In response to receipt by the node controller of a request transaction transmitted from the local processing node, via the node interconnect, the node controller at the remote processing node issues the request transaction on the local interconnect. If the request transaction receives a retry response at the remote processing node, the node controller reissues the request transaction on the local interconnect at least once, thus giving the request transaction another opportunity to complete successfully.

Abstract: The invention presents a method for selecting test cases in a test simulation of logic designs to improve speed and effectiveness of such testing. The method for selecting such test cases after such test cases are generated includes generating a test-coverage file and a harvest-goals file for the test case. The harvest-goals file contains a list of events and initial goal for each event. Harvest criteria is used to determined whether the number of hits for each event meets the initial goal. By applying the harvest criteria to the test case, it is determined whether to harvest the test case. The test case is saved and identified for harvest, if the test case is determined to be harvested. Also, the harvest-goals file is adjusted, if the test case is determined to be harvested.

Abstract: Speech Label Accelerators (SLAs) are provided that comprise an indirect memory, atom value memory, and adder circuitry. Optionally, the SLAs also comprise an accumulator, a load/accumulate multiplexer (mux), and a control unit. There are a variety of different configurations for the adder circuitry, and a configuration can be selected based on speed, power, and area requirements. A number of techniques are provided that allow a system having an SLA to handle more dimensions, atoms, or both than the SLA was originally designed for. A “zig-zag” method is provided that speeds processing in a system when using more dimensions than the SLA was originally designed for. Generally, the kernels used by the SLA will be Gaussian and separable, but non-Gaussian kernels and partially separable kernels may also be used by the SLA.

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node.

Abstract: A method for supporting software partition and dynamic reconfiguration within a non-uniform memory access (NUMA) computer system is disclosed. A NUMA computer system includes multiple nodes coupled to an interconnect. Each of the nodes includes a NUMA bridge, a local system memory, and at least one processor having at least a local cache memory. Multiple groups of software partitions are formed within the NUMA computer system, and each of the software partitions is formed by a subset of the nodes. A destination map table is provided in a NUMA bridge of each of the nodes for keeping track of the nodes within a software partition. A command is forwarded to only the nodes within a software partition.

Abstract: A non-uniform memory access (NUMA) computer system includes a plurality of processing nodes coupled to a node interconnect. The plurality of processing nodes include at least a remote processing node, which contains a processor having an associated cache hierarchy, and a home processing node. The home processing node includes a shared system memory containing a plurality of memory granules and a coherence directory that indicates possible coherence states of copies of memory granules among the plurality of memory granules that are stored within at least one processing node other than the home processing node. If the processor within the remote processing node has a reservation for a memory granule among the plurality of memory granules that is not resident within the associated cache hierarchy, the coherence directory associates the memory granule with a coherence state indicating that the reserved memory granule may possibly be held non-exclusively at the remote processing node.

Abstract: A non-uniform memory access (NUMA) computer system includes first and second processing nodes that are coupled together. The first processing node includes a system memory and first and second processors that each have a respective associated cache hierarchy. The second processing node includes at least a third processor and a system memory. If the cache hierarchy of the first processor holds an unmodified copy of a cache line and receives a request for the cache line from the third processor, the cache hierarchy of the first processor sources the requested cache line to the third processor and retains a copy of the cache line in a Recent coherency state from which the cache hierarchy of the first processor can source the cache line in response to subsequent requests.

Abstract: A system and method are provided which include devices implementing a snooping protocol. Data to be written by an I/O peripheral to an I/O controller is mapped to a specific location in memory, and then the data is actually written to an L1 cache in the controller by the I/O device. During this period when the I/O device is writing to the controller cache, the controller does not actually own the data stored in the specific memory location. Once the write operation is complete for a given memory sector, the I/O controller then performs the bus operations required to obtain ownership of the data in the specified memory location. The data read from memory is then merged with the data written from the I/O device and written back to the memory. If a snoop hit is identified by the I/O controller, during the period when the data is owned the I/O controller intervenes to prevent the memory access which caused the snoop hit.

Abstract: A method and system in a data processing system for transferring data from a first device to a second device within the data processing system. The data processing system includes a data bus, an address bus, a first address space associated with a memory and a second address space associated with an input/output device. Initially, a transfer signal is transmitted in the data processing system. The transfer signal identifies the transfer as a transfer concerning an address in the second address space associated with the input/output device. A first address package is then transmitted to the second device from the first device on the address bus. The first address package includes a transfer identifier, a first identifier associated with the first device and a second identifier associated with the second device. A second address package, comprising a byte count and an address, are transmitted to the second device from the first device on the address bus.