Abstract: The present disclosure relates to a graphics processor and a method of operating a graphics processing system for rendering a frame that represents a view of a scene comprising one or more objects using a ray tracing process. A traversal of a ray tracing acceleration data structure indicative of the distribution of geometry for the scene being rendered is performed to determine a first end node associated with a first internal node that will be intersected by a ray and requests data associated with the first end node from the local memory as well as requesting a prefetch of data associated with a second node of the plurality of nodes to be stored in the local memory, and determines, by testing the ray for intersection with the first end node, if the first end node is intersected by the ray.

Abstract: A graphics processor operable to render frames that represent a view of a scene using a ray tracing process includes a ray tracing circuit operable to test rays against a ray tracing acceleration data structure for a ray tracing process. The ray tracing circuit comprises a ray testing circuit operable to perform ray intersection tests for nodes of a ray tracing acceleration data structure and storage local to the ray testing circuit for storing data representative of one or more nodes of a ray tracing acceleration data structure for use by the ray testing circuit. Rays for testing by the ray testing circuit are selected from a pool of one or more rays to be tested based on an indication of the ray tracing acceleration data structure node or nodes that have been stored in the local storage of the ray testing circuit.

Abstract: A graphics processing system that is operable to perform ray tracing using micromaps is disclosed. First information representative of a micromap is used to determine whether further information should be fetched and used to determine a property value defined by the micromap. The first information may represent a coarse representation of the micromap, and the further information may represent a finer representation of the primitive.

Abstract: A graphics processor that is operable to generate a render output by performing a ray tracing process in which rays are traced through a scene to be rendered includes a programmable execution unit operable to execute graphics processing programs to perform rendering that includes performing a ray tracing process, a ray tracing circuit operable to test rays against a ray tracing acceleration data structure for a ray tracing process, and a programmable processing unit associated with and in communication with the ray tracing circuit, and configured to execute processing programs to perform processing relating to the operation of the ray tracing circuit.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: A graphics processor operable to render frames that represent a view of a scene using a ray tracing process includes a ray tracing circuit operable to test rays against a ray tracing acceleration data structure for a ray tracing process. The ray tracing circuit comprises a ray testing circuit operable to perform ray intersection tests for nodes of a ray tracing acceleration data structure and storage local to the ray testing circuit for storing data representative of one or more nodes of a ray tracing acceleration data structure for use by the ray testing circuit. Rays for testing by the ray testing circuit are selected from a pool of one or more rays to be tested based on an indication of the ray tracing acceleration data structure node or nodes that have been stored in the local storage of the ray testing circuit.

Abstract: A cache is provided having a plurality of entries for storing data. In response to a given access request, lookup circuitry performs a lookup operation in the cache to determine whether one of the entries in the cache is allocated to store data associated with the memory address indicated by the given access request, with a hit indication or a miss indication being generated dependent on the outcome of that lookup operation. During a single lookup period, the lookup circuitry is configured to perform lookup operations in parallel for up to N access requests. In addition, allocation circuitry is provided that is able to determine, during the single lookup period, at least N candidate entries for allocation from amongst the plurality of entries, and to cause one of the candidate entries to be allocated for each of the up to N access requests for which the lookup circuitry generates a miss indication.

Abstract: A cache is provided having a plurality of entries for storing data. In response to a given access request, lookup circuitry performs a lookup operation in the cache to determine whether one of the entries in the cache is allocated to store data associated with the memory address indicated by the given access request, with a hit indication or a miss indication being generated dependent on the outcome of that lookup operation. During a single lookup period, the lookup circuitry is configured to perform lookup operations in parallel for up to N access requests. In addition, allocation circuitry is provided that is able to determine, during the single lookup period, at least N candidate entries for allocation from amongst the plurality of entries, and to cause one of the candidate entries to be allocated for each of the up to N access requests for which the lookup circuitry generates a miss indication.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: Data processing apparatuses and methods for performing an iterative determination of a key schedule are provided. A set of registers initially receives an input data item and data processing is then performed using the content of the set of registers as an input. The result of this data processing is then used to update a value stored in a predetermined register of the set of registers at each iterative round of the determination of the key schedule. Dependent on whether the data processing apparatus is in a reverse key expansion mode or a forwards key expansion mode determines which register in the set of registers is that predetermined register. Further, the set of registers is arranged to shift values contained in the set of registers in a direction which depends on whether the data processing apparatus is in a reverse key expansion mode or a forwards key expansion mode. The directions for the two modes are opposite to one another.

Abstract: Data processing apparatuses and methods for performing an iterative determination of a key schedule are provided. A set of registers initially receives an input data item and data processing is then performed using the content of the set of registers as an input. The result of this data processing is then used to update a value stored in a predetermined register of the set of registers at each iterative round of the determination of the key schedule. Dependent on whether the data processing apparatus is in a reverse key expansion mode or a forwards key expansion mode determines which register in the set of registers is that predetermined register. Further, the set of registers is arranged to shift values contained in the set of registers in a direction which depends on whether the data processing apparatus is in a reverse key expansion mode or a forwards key expansion mode. The directions for the two modes are opposite to one another.