Abstract: A cache is provided having a plurality of entries for storing data. In response to a given access request, lookup circuitry performs a lookup operation in the cache to determine whether one of the entries in the cache is allocated to store data associated with the memory address indicated by the given access request, with a hit indication or a miss indication being generated dependent on the outcome of that lookup operation. During a single lookup period, the lookup circuitry is configured to perform lookup operations in parallel for up to N access requests. In addition, allocation circuitry is provided that is able to determine, during the single lookup period, at least N candidate entries for allocation from amongst the plurality of entries, and to cause one of the candidate entries to be allocated for each of the up to N access requests for which the lookup circuitry generates a miss indication.

Abstract: A cache is provided having a plurality of entries for storing data. In response to a given access request, lookup circuitry performs a lookup operation in the cache to determine whether one of the entries in the cache is allocated to store data associated with the memory address indicated by the given access request, with a hit indication or a miss indication being generated dependent on the outcome of that lookup operation. During a single lookup period, the lookup circuitry is configured to perform lookup operations in parallel for up to N access requests. In addition, allocation circuitry is provided that is able to determine, during the single lookup period, at least N candidate entries for allocation from amongst the plurality of entries, and to cause one of the candidate entries to be allocated for each of the up to N access requests for which the lookup circuitry generates a miss indication.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: Data processing apparatuses and methods for performing an iterative determination of a key schedule are provided. A set of registers initially receives an input data item and data processing is then performed using the content of the set of registers as an input. The result of this data processing is then used to update a value stored in a predetermined register of the set of registers at each iterative round of the determination of the key schedule. Dependent on whether the data processing apparatus is in a reverse key expansion mode or a forwards key expansion mode determines which register in the set of registers is that predetermined register. Further, the set of registers is arranged to shift values contained in the set of registers in a direction which depends on whether the data processing apparatus is in a reverse key expansion mode or a forwards key expansion mode. The directions for the two modes are opposite to one another.

Abstract: Data processing apparatuses and methods for performing an iterative determination of a key schedule are provided. A set of registers initially receives an input data item and data processing is then performed using the content of the set of registers as an input. The result of this data processing is then used to update a value stored in a predetermined register of the set of registers at each iterative round of the determination of the key schedule. Dependent on whether the data processing apparatus is in a reverse key expansion mode or a forwards key expansion mode determines which register in the set of registers is that predetermined register. Further, the set of registers is arranged to shift values contained in the set of registers in a direction which depends on whether the data processing apparatus is in a reverse key expansion mode or a forwards key expansion mode. The directions for the two modes are opposite to one another.