Abstract: Combining predictions made by multiple different prediction systems, including: obtaining a new input sample; obtaining a combiner which comprises optimal selection values that are configured to maximize a predefined performance measure; automatically applying multiple different prediction systems to the new input sample, to generate predictions; and automatically selectively combining the generated predictions based on the optimal selection values, to generate a combined prediction whose predefined performance measure is improved compared to individual usage of each of the prediction systems.

Abstract: Combining predictions made by multiple different prediction systems, including: obtaining a new input sample; obtaining a combiner which comprises optimal selection values that are configured to maximize a predefined performance measure; automatically applying multiple different prediction systems to the new input sample, to generate predictions; and automatically selectively combining the generated predictions based on the optimal selection values, to generate a combined prediction whose predefined performance measure is improved compared to individual usage of each of the prediction systems.

Abstract: A computerized apparatus, method and computer product for generating tests. The apparatus comprises: a processor; an interface for obtaining a test template associated with a computerized system that comprises a template segment comprising instructions and directives or related control constructs; a test generator for generating a test associated with the template segment, comprising: a simulator for determining a state of the system associated with an execution of the test; a selector for selecting a template instruction or segment from the test template based on the state of the system; and a generator configured to generate a multiplicity of instructions based on system's state and on the selected template segment, wherein the test generator further comprises a verifier configured to verify that a previously generated instruction is in line with the current state of the system and with the selected template instruction or segment.

Abstract: A computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.

Abstract: a computer-implemented method, an apparatus and a computer program for automatically extracting useful information for functional verification. The method comprising performing repeatedly both operating an instruction generator associated with a Design Under Test (DUT), whereby a generated instruction is determined, the generated instruction having one or more instruction attributes; and collecting information relating to the generated instruction. Based on the generated instruction and the collected information, a classification technique is utilized to classify the information based on the instruction attributes.

Abstract: Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.

Abstract: Generation of a test based on a test template comprising of branch instructions. The test template may be a layout test template, defining a set of possible control flows possibilities between template instructions in the layout test template. The test is generated by a test generator which may simulate a state of a target computerized system executing the test. The simulation may be performed during generation of the test. The test generator may further verify previously generated instructions. The test generator may further generate instructions associated with leftover template instructions.

Abstract: A computer-implemented method for verification of a hardware design includes specifying requests to allocate regions in a memory of the hardware design, such that at least two of the requests are specified independently of one another. The requests indicate respective allocation types. Overlap restrictions are specified between at least some of the allocation types. The requests and the overlap restrictions are automatically converted to a constraint satisfaction problem (CSP), which includes CSP constraints based on the requests, the allocation types and the overlap restrictions. The CSP is solved to produce a random test program, which includes a memory map that allocates the regions in the memory while complying with the requests and the overlap restrictions. The test program is applied to the hardware design.

Abstract: Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.

Abstract: Device, system and method of verification of address translation mechanisms. For example, an apparatus for testing an address translation mechanism of a design-under-test, the apparatus including: a test generator to receive a specification of at least one address translation table, and to generate one or more constraint-satisfaction-problem projectors over a plurality of attributes of said address translation table.

Abstract: A computer-implemented method for verification of a hardware design includes specifying requests to allocate regions in a memory of the hardware design, such that at least two of the requests are specified independently of one another. The requests indicate respective allocation types. Overlap restrictions are specified between at least some of the allocation types. The requests and the overlap restrictions are automatically converted to a constraint satisfaction problem (CSP), which includes CSP constraints based on the requests, the allocation types and the overlap restrictions. The CSP is solved to produce a random test program, which includes a memory map that allocates the regions in the memory while complying with the requests and the overlap restrictions. The test program is applied to the hardware design.