Abstract: The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.

Abstract: The disclosure relates to a traffic scheduling device for scheduling a transmission sequence of data packets, stored in a plurality of traffic flow queues, an eligibility state of each of the traffic flow queues for the scheduling is being maintained in a hierarchical scheduling database describing a relationship among the plurality of traffic flow queues. The traffic scheduling device includes: a plurality of interconnected memory cluster units. Each memory cluster unit is associated to a single or more levels of the hierarchical scheduling database and each memory cluster unit is coupled to at least one co-processors. At least one co-processor is software-programmable to implement a scheduling algorithm. The traffic scheduling device also includes an interface to the plurality of traffic flow queues.

Abstract: The disclosure relates to a traffic scheduling device for scheduling a transmission sequence of data packets, stored in a plurality of traffic flow queues, an eligibility state of each of the traffic flow queues for the scheduling is being maintained in a hierarchical scheduling database describing a relationship among the plurality of traffic flow queues. The traffic scheduling device includes: a plurality of interconnected memory cluster units. Each memory cluster unit is associated to a single or more levels of the hierarchical scheduling database and each memory cluster unit is coupled to at least one co-processors. At least one co-processor is software-programmable to implement a scheduling algorithm. The traffic scheduling device also includes an interface to the plurality of traffic flow queues.

Abstract: The disclosure relates to a traffic scheduling device for scheduling a transmission sequence of data packets, stored in a plurality of traffic flow queues, an eligibility state of each of the traffic flow queues for the scheduling is being maintained in a hierarchical scheduling database describing a relationship among the plurality of traffic flow queues. The traffic scheduling device includes: a plurality of interconnected memory cluster units. Each memory cluster unit is associated to a single or more levels of the hierarchical scheduling database and each memory cluster unit is coupled to at least one co-processors. At least one co-processor is software-programmable to implement a scheduling algorithm. The traffic scheduling device also includes an interface to the plurality of traffic flow queues.

Abstract: The invention relates to a scheduling device for receiving a set of requests and providing a set of grants to the set of requests, the scheduling device comprising: a lookup vector prepare unit configured to provide a lookup vector prepared set of requests depending on the set of requests and a selection mask and to provide a set of acknowledgements to the set of requests; and a prefix forest unit coupled to the lookup vector prepare unit, wherein the prefix forest unit is configured to provide the set of grants as a function of the lookup vector prepared set of requests and to provide the selection mask based on the set of grants.

Abstract: The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.

Abstract: Bacterial, yeast and animal cells and methods for overexpressing recombinant heparanase in cellular systems, methods of purifying recombinant heparanase therefrom and modified heparanase species which serve as precursors for generating highly active heparanase by proteolysis.

Abstract: Bacterial, yeast and animal cells and methods for overexpressing recombinant heparanase in cellular systems, methods of purifying recombinant heparanase therefrom and modified heparanase species which serve as precursors for generating highly active heparanase by proteolysis.

Abstract: Qualitative and quantitative methods of testing an agent for its potential at inhibiting glycosidase catalytic activity, the methods including the steps of interacting a glycosidase enzyme with a glycosidase substrate in a presence of the agent and qualitatively or quantitatively evaluating an effect of the agent on the catalytic activity of the glycosidase enzyme toward the glycosidase substrate. Preferably the glycosidase enzyme is a heparanase enzyme and the glycosidase substrate is, respectively, a heparanase substrate.