Patents by Inventor Yoav Talgam
Yoav Talgam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9600995Abstract: Embodiments are generally directed to a wearable electronic device providing injury response. A wearable electronic device may include an injury detection unit that includes one or more sensors, and a central computing unit to receive sensor data from the one or more sensors to detect one or more injuries or potential injuries based at least in part on the received sensor data. The wearable electronic device further includes an injury response unit to provide a response to the one or more injuries or potential injuries.Type: GrantFiled: June 26, 2015Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Tamara Gaidar, Glen J. Anderson, Yoav Talgam, Stephen Brown, Ido Lapidot, Oded Agam
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Patent number: 9588771Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.Type: GrantFiled: March 8, 2013Date of Patent: March 7, 2017Assignee: Intel CorporationInventors: Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James P. Held
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Publication number: 20160379461Abstract: Embodiments are generally directed to a wearable electronic device providing injury response. A wearable electronic device may include an injury detection unit that includes one or more sensors, and a central computing unit to receive sensor data from the one or more sensors to detect one or more injuries or potential injuries based at least in part on the received sensor data. The wearable electronic device further includes an injury response unit to provide a response to the one or more injuries or potential injuries.Type: ApplicationFiled: June 26, 2015Publication date: December 29, 2016Inventors: Tamara Gaidar, Glen J. Anderson, Yoav Talgam, Stephen Brown, Ido Lapidot, Oded Agam
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Patent number: 9459874Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.Type: GrantFiled: November 14, 2014Date of Patent: October 4, 2016Assignee: Intel CorporationInventors: Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James P. Held
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Publication number: 20150070368Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.Type: ApplicationFiled: November 14, 2014Publication date: March 12, 2015Inventors: Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James P. Held
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Patent number: 8914618Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.Type: GrantFiled: December 29, 2005Date of Patent: December 16, 2014Assignee: Intel CorporationInventors: Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James P. Held
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Publication number: 20130205122Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.Type: ApplicationFiled: March 8, 2013Publication date: August 8, 2013Inventors: Hong WANG, John SHEN, Hong JIANG, Richard HANKINS, Per HAMMARLUND, Dion RODGERS, Gautham CHINYA, Baiju PATEL, Shiv KAUSHIK, Bryant BIGBEE, Gad SHEAFFER, Yoav Talgam, Yuval YOSEF, James P. HELD
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Publication number: 20070157211Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.Type: ApplicationFiled: December 29, 2005Publication date: July 5, 2007Inventors: Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James Held
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Patent number: 5067078Abstract: A first processing system is coupled to a plurality of integrated circuits along a P bus. Each of these integrated circuits has a combination cache and memory management unit (MMU). The cache/MMU integrated circuits are also connected to a main memory via an M bus. A second processing system is also coupled to the main memory primarily via a secondary bus but also via the M bus. External TAGs coupled between the M bus and the secondary bus are used to maintain coherency between the first and second processing systems. Each external TAG corresponds to a particular cache/MMU integrated circuit and maintains information as to the status of its corresponding cache/MMU integrated circuit. The cache/MMU integrated circuit provides the necessary status information to its corresponding external TAG in a very efficient manner. Each cache/MMU integrated circuit can also be converted to a SRAM mode in which the cache performs like a conventional high speed static random access memory (SRAM).Type: GrantFiled: April 17, 1989Date of Patent: November 19, 1991Assignee: Motorola, Inc.Inventors: Yoav Talgam, James A. Klingshirn, James B. Gullette
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Patent number: 4996641Abstract: A cache has an address bus for receiving requests for data from a processor and a data bus for providing the requested data to the processor. As part of the mechanism for determining if there is a hit in the cache, the cache has TAG locations for storing TAG addresses. The hit signal is not generated unless a TAG address corresponds to the address received on the address bus. Associated with each TAG location are valid bits, disable bits, and LRU bits. The requested data is contained in data locations in the cache. Each data location has a corresponding TAG location. The disable bits can be set under the control of the processor for the case where a data location is defective. Additionally, in various diagnostic modes, the TAG locations, the valid bits, the LRU bits, and the data locations are directly accessible via the data bus.Type: GrantFiled: April 15, 1988Date of Patent: February 26, 1991Assignee: Motorola, Inc.Inventors: Yoav Talgam, Paul A. Reed, Elie Haddad, James A. Klingshirn
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Patent number: 4914581Abstract: In a data processor, the conditions associated with an operand are evaluated only in response to the execution of a special instruction. The results of this evaluation is provided as a result operand and stored in a general purpose destination register. The evaluated conditions are each provided in discrete form, that is, unencoded, rather than in encoded form.Type: GrantFiled: October 26, 1987Date of Patent: April 3, 1990Assignee: Motorola, Inc.Inventors: Yoav Talgam, Mitch K. Alsup, James A. Klingshirn
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Patent number: 4903264Abstract: A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechanism if the output result cannot be provided in a selected format. Special buffers are also provided to allow the control and status information unique to each instruction to flow through the pipeline together with that instruction. Sufficient information relating to each instruction being executed in the data unit is retained and made readily available to the handlers, so that each type of exception may be handled, should recovery be possible.Type: GrantFiled: April 18, 1988Date of Patent: February 20, 1990Assignee: Motorola, Inc.Inventors: Yoav Talgam, Mitch K. Alsup, Marvin A. Denman
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Patent number: 4893267Abstract: In a data processor having an integer arithmetic unit, the carry-in control logic, carry-out control logic, and the overflow control logic of the arithmetic unit are adapted to be directly controlled by respective carry-in enable, carry-out enable, and overflow enable fields of the integer arithmetic instructions during the execution thereof.Type: GrantFiled: November 1, 1988Date of Patent: January 9, 1990Assignee: Motorola, Inc.Inventors: Mitchell Alsup, Yoav Talgam, Marvin A. Denman
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Patent number: 4893233Abstract: A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechanism if the output result cannot be provided in a selected format. Special buffers are also provided to allow the control and status information unique to each instruction to flow through the pipeline together with that instruction. Sufficient information relating to each instruction being executed in the data unit is retained and made readily available to the handlers, so that each type of exception may be handled, should recovery be possible.Type: GrantFiled: April 18, 1988Date of Patent: January 9, 1990Assignee: Motorola, Inc.Inventors: Denman Marvin A., Yoav Talgam