Abstract: A system and method are provided for generating Unique Digital Signatures (UDS) for semiconductor memories to improve data security. Generally, the method involves allocating a number of native memory cells in a memory device; obtaining a multibit binary entropy string (BES) using variations of threshold voltages (VT) of the allocated cells as an entropy source; and mathematically manipulating the BES to generate the UDS. Optionally, the BES can be concatenated with another multibit binary number from a second entropy source internal or external to the memory device, and the result of the concatenation mathematically manipulated to generate the UDS. In one embodiment, a reference voltage is located at a median VT for the cells, and the BES is obtained by reading the cells versus the reference, assigning those having a VT above the reference a first bit value, and the remaining cells a second bit value.

Abstract: Controlling an etch process applied to a multi-layered structure, by calculating a spectral derivative of reflectance of an illuminated region of interest of a multi-layered structure during an etch process applied to the multi-layered structure, identifying in the spectral derivative a discontinuity that indicates that an edge of a void formed by the etch process at the region of interest has crossed a layer boundary of the multi-layered structure, determining that the crossed layer boundary corresponds to a preselected layer boundary of the multi-layered structure, and applying a predefined control action to the etch process responsive to determining that the crossed layer boundary corresponds to the preselected layer boundary of the multi-layered structure.

Abstract: In an embodiment, a method includes: receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a programing pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from transistor-based memory cells associated with the plurality of redundant bit addresses; when one of the first bit value and the redundant bit values do not match the first write value, determining a majority bit value based on the first bit value and on the redundant bit values; and asserting a flag signal when the majority bit value does not match the first write value.

Abstract: Systems, methods, and devices implement counters with fault tolerance and power loss protection. Systems include a non-volatile memory device that includes a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing an initiation and a completion of each erase operation performed on the first counter. Systems also include control circuitry configured to generate a count value based on a current counter value of the first counter, a current counter value of the second counter, and at least one physical parameter of the first counter.

Abstract: Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells; a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.

Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells; a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.

Abstract: Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells: a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.

Abstract: A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array.

Abstract: A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array.

Abstract: A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array.

Abstract: Disclosed are methods, data-structures, circuits, devices and system for operating a non-volatile memory device. According to some embodiments, a controller may operate on different portions (e.g. clusters) of a NVM memory array differently, depending upon a designation of a given portion within a table stored on the array. Portions of the array may be operated in OTP page write mode, while other portions of the array may be operated in either bit level or byte level append modes.

Abstract: The invention provides a method of managing bad block in a data storage device having an OTP memory die in order to present a continues address space toward the user, by using some of the OTP memory space for the management and maintaining address replacement table. Fast and efficient programming and reading algorithms are presented.

Abstract: OTP Data storage die and device consisting of novel OTP (One-Time-Programming) NVM (Non-Volatile-Memory) die is disclosed. The OTP Data storage device can be used in typical host applications with standard interface protocols and file system. The novel OTP memory is a dual memory with both RAM (random access memory) capability and NAND Flash like interface. These features enable to achieve efficient management capabilities and dense array for the OTP data storage device.

Abstract: The invention provides a method of managing data updates in DOS-based data storage device having an OTP memory die that includes a code region having a first memory capacity and a code region access resolution and a data region having a second memory capacity and a data region access resolution. The second memory capacity is larger than the first memory capacity and the code region access resolution is finer than the data region access resolution. The method includes chronologically writing a log entry in the code region indicating the change in FAT and root directory for each change in user data written in the data region.

Abstract: The invention provides a method of managing data updates in DOS-based data storage device having an OTP memory die that includes a code region having a first memory capacity and a code region access resolution and a data region having a second memory capacity and a data region access resolution. The second memory capacity is larger than the first memory capacity and the code region access resolution is finer than the data region access resolution. The method includes chronologically writing a log entry in the code region indicating the change in FAT and root directory for each change in user data written in the data region.

Abstract: Disclosed is a circuit, system, device and method for authentication and/or encryption, which is based on the characteristics and/or management of One Time Programming (OTP) Non Volatile Memory (NVM) that may prevent the ability to alter, modify, mimic or otherwise use an identification string/code for attaining false authentication and/or falsely decrypting encrypted data.

Abstract: The invention provides a method of managing bad block in a data storage device having an OTP memory die in order to present a continues address space toward the user, by using some of the OTP memory space for the management and maintaining address replacement table. Fast and efficient programming and writing algorithms are presented.

Abstract: The invention provides a method of managing bad block in a data storage device having an OTP memory die in order to present a continues address space toward the user, by using some of the OTP memory space for the management and maintaining address replacement table. Fast and efficient programming and reading algorithms are presented.