Abstract: A Group III-V semiconductor device and a method of fabricating the same including an in-situ surface passivation layer. A two-stage cleaning process may be effectuated for cleaning a reactor chamber prior to growing one or more epitaxial layers and forming subsequent surface passivation layers, wherein a first cleaning process may involve a remotely generated plasma containing fluorine-based reactive species for removing SiXNY residual material accumulated in the reactor chamber and/or over any components disposed therein.

Abstract: GaN devices with a modified heterojunction structure and methods of making thereof are described. The GaN device comprises a heterojunction structure modified to include one or more deactivated regions. The heterojunction structure of the deactivated regions has different structural configurations than that of the as-grown heterojunction structure. The locally confined structural alteration of the heterojunction structure weakens or prohibits 2DEG formation in the deactivated regions. Moreover, the amount of net charges mapped to a field plate positioned above the heterojunction structure can be locally reduced or eliminated. Consequently, the electric field present between the heterojunction structure and the field plate can be reduced.

Abstract: A gallium nitride (GaN) transistor which includes multiple insulator semiconductor interface regions. Two or more first insulator segments and two or more second insulator segments are positioned between the gate and drain contacts and interleaved together. At least one first insulator segment is nearer to the gate contact than the second insulator segments. At least one second insulator segment is nearer to the drain contact than the first insulator segments. The first and second insulators are chosen such that a net electron donor density above the channel under the first insulator segments is lower than a net electron density above the channel under the second insulator segments. The first insulator segments reduce gate leakage and electric fields near the gate that cause high gate-drain charge. The second insulator segments reduce electric fields near the drain contact and provide a high density of charge in the channel for reduced on-resistance.

Abstract: A gallium nitride (GaN) transistor which includes multiple insulator semiconductor interface regions. Two or more first insulator segments and two or more second insulator segments are positioned between the gate and drain contacts and interleaved together. At least one first insulator segment is nearer to the gate contact than the second insulator segments. At least one second insulator segment is nearer to the drain contact than the first insulator segments. The first and second insulators are chosen such that a net electron donor density above the channel under the first insulator segments is lower than a net electron density above the channel under the second insulator segments. The first insulator segments reduce gate leakage and electric fields near the gate that cause high gate-drain charge. The second insulator segments reduce electric fields near the drain contact and provide a high density of charge in the channel for reduced on-resistance.

Abstract: An enhancement-mode transistor gate structure which includes a spacer layer of GaN disposed above a barrier layer, a first layer of pGaN above the spacer layer, an etch stop layer of p-type Al-containing column III-V material, for example, pAlGaN or pAlInGaN, disposed above the first p-GaN layer, and a second p-GaN layer, having a greater thickness than the first p-GaN layer, disposed over the etch stop layer. The etch stop layer minimizes damage to the underlying barrier layer during gate etching steps, and improves GaN spacer thickness uniformity.

Abstract: An example embodiment includes method for forming a layer of a Group III-Nitride material. The method includes providing a substrate having a main surface comprising a layer of a first Group III-nitride material. The substrate further includes, on the main surface, a dielectric layer comprising an opening exposing the first Group III-nitride material. A thermal treatment process is performed while subjecting the substrate to a gas mixture comprising a nitrogen containing gas, thereby increasing temperature of the substrate up to a temperature for growing a layer of a second Group III-nitride material. At least one Group III-metal organic precursor gas is subsequently introduced into the gas mixture at the growth temperature, thereby forming, at least in the opening on the exposed Group III-nitride material, a layer of the second Group III-nitride material by selective epitaxial growth, characterized in that the gas mixture is free of hydrogen gas.

Abstract: The present disclosure is related to a III-Nitride semiconductor device comprising a base substrate, a buffer layer, a channel layer, a barrier layer so that a 2-dimensional charge carrier gas is formed or can be formed near the interface between the channel layer and the barrier layer, and at least one set of a first and second electrode in electrical contact with the 2-dimensional charge carrier gas, wherein the device further comprises a mobile charge layer (MCL) within the buffer layer or near the interface between the buffer layer and the channel layer, when the device is in the on-state. The device further comprises an electrically conductive path between one of the electrodes and the mobile charge layer. The present disclosure is also related to a method for producing a device according to the present disclosure.

Abstract: An enhancement-mode transistor gate structure which includes a spacer layer of GaN disposed above a barrier layer, a first layer of pGaN above the spacer layer, an etch stop layer of p-type Al-containing column III-V material, for example, pAlGaN or pAlInGaN, disposed above the first p-GaN layer, and a second p-GaN layer, having a greater thickness than the first p-GaN layer, disposed over the etch stop layer. The etch stop layer minimizes damage to the underlying barrier layer during gate etching steps, and improves GaN spacer thickness uniformity.

Abstract: An example embodiment includes method for forming a layer of a Group III-Nitride material. The method includes providing a substrate having a main surface comprising a layer of a first Group III-nitride material. The substrate further includes, on the main surface, a dielectric layer comprising an opening exposing the first Group III-nitride material. A thermal treatment process is performed while subjecting the substrate to a gas mixture comprising a nitrogen containing gas, thereby increasing temperature of the substrate up to a temperature for growing a layer of a second Group III-nitride material. At least one Group III-metal organic precursor gas is subsequently introduced into the gas mixture at the growth temperature, thereby forming, at least in the opening on the exposed Group III-nitride material, a layer of the second Group III-nitride material by selective epitaxial growth, characterized in that the gas mixture is free of hydrogen gas.

Abstract: The present disclosure is related to a III-Nitride semiconductor device comprising a base substrate, a buffer layer, a channel layer, a barrier layer so that a 2-dimensional charge carrier gas is formed or can be formed near the interface between the channel layer and the barrier layer, and at least one set of a first and second electrode in electrical contact with the 2-dimensional charge carrier gas, wherein the device further comprises a mobile charge layer (MCL) within the buffer layer or near the interface between the buffer layer and the channel layer, when the device is in the on-state. The device further comprises an electrically conductive path between one of the electrodes and the mobile charge layer. The present disclosure is also related to a method for producing a device according to the present disclosure.

Abstract: A method and apparatus for adjust local plasma density during a plasma process. One embodiment provides an electrode assembly comprising a conductive faceplate having a nonplanar surface. The nonplanar surface is configured to face a substrate during processing and the conductive faceplate is disposed so that the nonplanar surface is opposing a substrate support having an electrode. The conductive faceplate and the substrate support form a plasma volume. The nonplanar surface is configured to adjust electric field between the conductive plate and the electrode by varying a distance between the conductive plate and the electrode.

Abstract: A method and apparatus for adjust local plasma density during a plasma process. One embodiment provides an electrode assembly comprising a conductive faceplate having a nonplanar surface. The nonplanar surface is configured to face a substrate during processing and the conductive faceplate is disposed so that the nonplanar surface is opposing a substrate support having an electrode. The conductive faceplate and the substrate support form a plasma volume. The nonplanar surface is configured to adjust electric field between the conductive plate and the electrode by varying a distance between the conductive plate and the electrode.