Patents by Inventor Yogesh B
Yogesh B has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12366965Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.Type: GrantFiled: September 27, 2023Date of Patent: July 22, 2025Assignee: SK hynix NAND Product Solutions CorporationInventors: David J. Pelster, Yogesh B. Wakchaure, Neelesh Vemula, Aliasgar S. Madraswala, David B. Carlton, Donia Sebastian, Mark Anthony Golez, Xin Guo
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Patent number: 12353752Abstract: An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, maintain respective read disturb (RD) counters for each of two or more tracked units at respective granularities, maintain respective global RD counters for each of the two or more tracked units and, in response to a read request, increment one or more global RD counters that correspond to the read request, determine if a global RD counter for a tracked unit matches a random number associated with the tracked unit and, if so determined, increment a RD counter for the tracked unit that corresponds to the read request and generate a new random number for the tracked unit. Other embodiments are disclosed and claimed.Type: GrantFiled: September 22, 2021Date of Patent: July 8, 2025Inventors: Mohammad Nasim Imtiaz Khan, Yogesh B. Wakchaure, Eric Hoffman, Neal Mielke, Shirish Bahirat, Cole Uhlman, Ye Zhang, Anand Ramalingam
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Patent number: 12230334Abstract: Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller determines that the program operation can be initiated without loading all pages into the memory. In response, the NAND loads a first page and then executes portions of the program operation in parallel, at least in part, with loading subsequent pages. The NAND behavior is modified to monitor data loading completion times, to copy pages from a cache register to a data register as needed, and to resume program operation if a shutdown occurs. The portions of the program operation include a program prologue operation and a pulse verify loop for the first voltage level (L1) of the MLC memory.Type: GrantFiled: March 31, 2022Date of Patent: February 18, 2025Assignee: Intel NDTM US LLCInventors: Aliasgar S. Madraswala, Ali Khakifirooz, Bhaskar Venkataramaiah, Sagar Upadhyay, Yogesh B. Wakchaure
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Patent number: 12206566Abstract: Techniques are described for monitoring application performance in a computer network. For example, a network management system (NMS) includes a memory storing path data received from a plurality of network devices, the path data reported by each network device of the plurality of network devices for one or more logical paths of a physical interface from the given network device over a wide area network (WAN). Additionally, the NMS may include processing circuitry in communication with the memory and configured to: determine, based on the path data, one or more application health assessments for one or more applications, wherein the one or more application health assessments are associated with one or more application time periods for a site, and in response to determining at least one failure state, output a notification including identification of a root cause of the at least one failure state.Type: GrantFiled: January 17, 2023Date of Patent: January 21, 2025Assignee: Juniper Networks, Inc.Inventors: Prashant Kumar, Jisheng Wang, Gorakhanath Kathare, Yogesh B G, Kaushik Adesh Agrawal, Jie C Jiang, Scott A. McCulley, Greg Schrock
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Patent number: 12184522Abstract: Techniques are described for monitoring application performance in a computer network. For example, a network management system (NMS) includes a memory storing path data received from a plurality of network devices, the path data reported by each network device of the plurality of network devices for one or more logical paths of a physical interface from the given network device over a wide area network (WAN). Additionally, the NMS may include processing circuitry in communication with the memory and configured to: determine, based on the path data, one or more application health assessments for one or more applications, wherein the one or more application health assessments are associated with one or more application time periods for a site, and in response to determining at least one failure state, output a notification including identification of a root cause of the at least one failure state.Type: GrantFiled: January 17, 2023Date of Patent: December 31, 2024Assignee: Juniper Networks, Inc.Inventors: Prashant Kumar, Jisheng Wang, Gorakhanath Kathare, Yogesh B G, Kaushik Adesh Agrawal, Jie C Jiang, Scott A. McCulley, Greg Schrock
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Publication number: 20240422085Abstract: Techniques are described for monitoring application performance in a computer network. For example, a network management system (NMS) includes a memory storing path data received from a plurality of network devices, the path data reported by each network device of the plurality of network devices for one or more logical paths of a physical interface from the given network device over a wide area network (WAN). Additionally, the NMS may include processing circuitry in communication with the memory and configured to: determine, based on the path data, one or more application health assessments for one or more applications, wherein the one or more application health assessments are associated with one or more application time periods for a site, and in response to determining at least one failure state, output a notification including identification of a root cause of the at least one failure state.Type: ApplicationFiled: August 23, 2024Publication date: December 19, 2024Inventors: Prashant Kumar, Jisheng Wang, Gorakhanath Kathare, Yogesh B G, Kaushik Adesh Agrawal, Jie C Jiang, Scott A. McCulley, Greg Schrock
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Patent number: 12154620Abstract: A method and apparatus to reduce read retry operations in a NAND Flash memory is provided. To reduce the number of read retries for future reads, a word line group is assigned an optimal read voltage, the reference voltage that results in eliminating the read error for the word line is selected as the optimal read voltage (also referred to as a “sticky voltage”) for the word line group to be used for a next read of the page. An optimal read voltage per word line group for the page per NAND Flash memory die is stored in the lookup table. Storing an optimal read voltage per word line group instead of per die reduces the number of read retries.Type: GrantFiled: September 27, 2019Date of Patent: November 26, 2024Assignee: SK hynix NAND Product Solutions Corp.Inventors: Lei Chen, Yogesh B. Wakchaure, Aliasgar S. Madraswala, Xin Guo, Cole Uhlman
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Publication number: 20240347117Abstract: An apparatus is described. The apparatus includes a memory chip having logic circuitry to suspend application of an erasure voltage, wherein, respective responses of the erasure voltage to a decision to suspend the application of the erasure voltage depend on where the erasure voltage is along its waveform.Type: ApplicationFiled: June 24, 2024Publication date: October 17, 2024Inventors: Justin R. Dayacap, Shantanu R. Rajwade, Kyung Jean Yoon, Ali Khakifirooz, David J. Pelster, Yogesh B. Wakchaure, Xin Guo
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Patent number: 12092620Abstract: An improved gas chromatography system is presented. The system comprises: an enclosure having an inlet and an outlet, such that the ventilation flow is from the inlet to the outlet; a chamber disposed in the enclosure; a monolithic gas analyzer disposed in the chamber and a temperature control unit disposed in physical contact with the chamber. The monolithic gas analyzer operates to separate and detect molecules from a gas; whereas, the temperature control unit is configured to control temperature inside the chamber.Type: GrantFiled: July 3, 2019Date of Patent: September 17, 2024Assignee: Omniscent Inc.Inventors: Yutao Qin, Yogesh B. Gianchandani
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Patent number: 12051472Abstract: An apparatus is described. The apparatus includes a memory chip having logic circuitry to suspend application of an erasure voltage, wherein, respective responses of the erasure voltage to a decision to suspend the application of the erasure voltage depend on where the erasure voltage is along its waveform.Type: GrantFiled: December 26, 2019Date of Patent: July 30, 2024Assignee: SK hynix NAND Product Solutions Corp.Inventors: Justin R. Dayacap, Shantanu R. Rajwade, Kyung Jean Yoon, Ali Khakifirooz, David J. Pelster, Yogesh B. Wakchaure, Xin Guo
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Publication number: 20240249869Abstract: A radio frequency (RF) matching system may include an airflow generator configured to generate an airflow stream and an induction coil apparatus positioned within the airflow stream to be generated by the airflow generator. The induction coil apparatus may include an induction coil and an airflow guide positioned and configured to direct the airflow stream to be generated by the airflow generator over the induction coil. The airflow generator may be downstream or upstream of the induction coil apparatus in the airflow stream to be generated by the airflow generator.Type: ApplicationFiled: January 19, 2024Publication date: July 25, 2024Inventors: Ronald Anthony DECKER, Yogesh B. JAGDALE
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Publication number: 20240249916Abstract: In one embodiment, a variable capacitance apparatus is disclosed. The variable capacitance apparatus includes a support structure and a plurality of capacitor units. The support structure has a platform, a plurality of walls extending upward from the platform, and a plurality of channels formed between adjacent ones of the walls. Each of the capacitor units has a capacitor and first and second capacitor leads. The plurality of capacitor units are mounted to the support structure so that the plurality of capacitors are positioned within the plurality of channels. Adjacent ones of the plurality of capacitors are separated from one another by one of the plurality of walls to prevent arcing therebetween.Type: ApplicationFiled: January 17, 2024Publication date: July 25, 2024Inventors: Ronald Anthony DECKER, Yogesh B. JAGDALE
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Patent number: 12044609Abstract: Investigating the permeability and porosity of geological samples is a routine element of geological studies, and is of particular interest in the oil and gas industry. Core-flood experiments are commonly performed on rock samples to measure transport characteristics in the laboratory. This disclosure reports the design and implementation of a high resolution distributed pressure measurement system for core-flood experiments. A series of microfabricated pressure sensors can be embedded in bolts that are housed within the pressurized polymer sheath that encases a rock core. A feedthrough technology has been developed to provide lead transfer between the sensors and system electronics across a 230-bar pressure difference. The system has been successfully benchtop tested with fluids such as synthetic oil and/or gas. Pressure measurements were recorded over a dynamic range of 20 bar with a resolution as small as 0.3 mbar.Type: GrantFiled: October 2, 2020Date of Patent: July 23, 2024Assignees: The Regents of The University of Michigan, TOTAL S.E.Inventors: Yogesh B. Gianchandani, Tao Li, Partha Dutta, Alexander Benken, John-Richard Ordonez-Varela
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Publication number: 20240123925Abstract: A system includes a graphical user interface display, a cockpit domain controller, and a wireless device. The graphical user interface display is operational to receive a plurality of input commands from an end user. The cockpit domain controller is in communication with the graphical user interface display, and is operational to transmit a plurality of wireless signals in response to the plurality of input commands received from the graphical user interface display. The wireless device is connectable to a controlled device, is in wireless communication with the cockpit domain controller, is operational to translate the plurality of wireless signals received from the cockpit domain controller into at least one of a motor control command and a switch control command, and is operational to present the at least one of the motor control command and the switch control command to the controlled device while connected.Type: ApplicationFiled: October 12, 2023Publication date: April 18, 2024Applicant: VISTEON GLOBAL TECHNOLOGIES, INC.Inventors: Gang Wei, Yogesh B. Patel, Antonio O. Odejerte
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Patent number: 11927574Abstract: A progressive cellular architectures has been presented for vapor-phase chemical analyzers. The progressive cellular architecture consists of a series of heterogeneous micro-gas chromatography cells. Each individual cell targets vapor species within a specific volatility range by using a unique combination of a preconcentrator and a separation column. The cells are connected progressively in series to cover a broad range of volatile analyte chemical vapors. Valves may inadvertently absorb or adsorb and subsequently release target chemical analyte molecules, thereby interfering with quantitative analysis. Therefore, the inlet to the cells is configured without a valve.Type: GrantFiled: December 14, 2020Date of Patent: March 12, 2024Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Yogesh B. Gianchandani, Yutao Qin, Weilin Liao, Hsueh-Tsung Lu, Declan Winship
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Publication number: 20240020013Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.Type: ApplicationFiled: September 27, 2023Publication date: January 18, 2024Inventors: David J. Pelster, Yogesh B. Wakchaure, Neelesh Vemula, Aliasgar S. Madraswala, David B. Carlton, Donia Sebastian, Mark Anthony Golez, Xin Guo
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Publication number: 20240011593Abstract: In various aspects, the present disclosure provides an example autonomous microsystem for immersion into a fluid. The autonomous microsystem includes electronics, a power source, and a packaging system that surrounds the electronics and the power source. The electronics can be configured to sense and record one or more environmental conditions. The packaging system may include a deformable shell that defines an internal space and a plurality of filler particles disposed in the internal space and configured to control a density of the autonomous microsystem in relation to the fluid. The filler particles may comprise a low-density material having a bulk density greater than or equal to about 100 kg/m3 and less than or equal to about 1,000 kg/m3 and have a packing density greater than or equal to about 1011/m3 and less than or equal to about 1021/m3.Type: ApplicationFiled: November 6, 2020Publication date: January 11, 2024Applicants: THE REGENTS OF THE UNIVERSITY OF MICHIGAN, TOTALENERGIES ONETECHInventors: Yogesh B. GIANCHANDANI, Alexander BENKEN, Neeharika VELLALURU, Partha DUTTA, John-Richard ORDONEZ-VARELA, Aurelie LE-BEULZE, Jean-Gregoire BOERO-ROLLO
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Patent number: 11797188Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.Type: GrantFiled: December 12, 2019Date of Patent: October 24, 2023Assignee: SK hynix NAND Product Solutions Corp.Inventors: David J. Pelster, Yogesh B. Wakchaure, Neelesh Vemula, Aliasgar S. Madraswala, David B. Carlton, Donia Sebastian, Mark Anthony Golez, Xin Guo
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Publication number: 20230317182Abstract: Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller determines that the program operation can be initiated without loading all pages into the memory. In response, the NAND loads a first page and then executes portions of the program operation in parallel, at least in part, with loading subsequent pages. The NAND behavior is modified to monitor data loading completion times, to copy pages from a cache register to a data register as needed, and to resume program operation if a shutdown occurs. The portions of the program operation include a program prologue operation and a pulse verify loop for the first voltage level (L1) of the MLC memory.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Aliasgar S. MADRASWALA, Ali KHAKIFIROOZ, Bhaskar VENKATARAMAIAH, Sagar UPADHYAY, Yogesh B. WAKCHAURE
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Publication number: 20230261930Abstract: Techniques are described for monitoring application performance in a computer network. For example, a network management system (NMS) includes a memory storing path data received from a plurality of network devices, the path data reported by each network device of the plurality of network devices for one or more logical paths of a physical interface from the given network device over a wide area network (WAN). Additionally, the NMS may include processing circuitry in communication with the memory and configured to: determine, based on the path data, one or more application health assessments for one or more applications, wherein the one or more application health assessments are associated with one or more application time periods for a site, and in response to determining at least one failure state, output a notification including identification of a root cause of the at least one failure state.Type: ApplicationFiled: January 17, 2023Publication date: August 17, 2023Inventors: Prashant Kumar, Jisheng Wang, Gorakhanath Kathare, Yogesh B G, Kaushik Adesh Agrawal, Jie C Jiang, Scott A. McCulley, Greg Schrock