Patents by Inventor Yogesh Gathoo

Yogesh Gathoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Computer aided design tool and user interface for configuration of a programmable system-on-a-chip
    Patent number: 8769477
    Abstract: A user interface for a computer-aided design tool includes a display. The display includes a visualization of a processor system of a system-on-a-chip (SOC). The visualization includes a plurality of blocks and each block represents a component of the processor system. Each block visually indicates a configuration status of the component represented by the block.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 1, 2014
    Assignee: Xilinx, Inc.
    Inventors: Yogesh Gathoo, Siddharth Rele, Gregory A. Brown, Avdhesh Palliwal, Gangadhar Budde, Sumit Nagpal
  • Nondestructive patching mechanism
    Patent number: 7984434
    Abstract: Techniques and mechanisms are provided for patching software, such as software for implementing parameterizable processor cores and peripherals on a programmable chip. Software components constructed using various shared modules can be updated without affecting other components using the same shared modules. In one example, a software component includes a manifest for identifying the implementations that should be associated with the various modules. When a patched implementation is provided for a particular module, the component manifest is changed to associate the patched implementation with the component. The pre-patch implementation is preserved so that other components using the pre-patch implementation may be kept unchanged.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: July 19, 2011
    Assignee: Altera Corporation
    Inventor: Yogesh Gathoo
  • Generating cores using secure scripts
    Patent number: 7574679
    Abstract: Methods and apparatus are provided for securely generating IP cores. A designer selects and configures parameterizable IP cores provided for implementation on a programmable chip. The IP cores are processed using mechanisms such as scripts to parameterize and customize the IP cores while removing option and parameter information.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: August 11, 2009
    Assignee: Altera Corporation
    Inventors: Yogesh Gathoo, Bradley Grove
  • Generating optimized and secure IP cores
    Patent number: 7165229
    Abstract: Methods and apparatus are provided for securely generating IP cores. A designer selects and configures parameterizable IP cores provided for implementation on a programmable chip. The IP cores are processed using mechanisms such as scripts to parameterize and customize the IP cores while removing option and parameter information. IP core, related scripts, and results are provided in encrypted form.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: January 16, 2007
    Assignee: Altera Corporation
    Inventors: Yogesh Gathoo, Bradley Grove