Patents by Inventor Yogesh Mittal

Yogesh Mittal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240073084
    Abstract: Techniques and architecture are described for a pull model for obtaining and implementing config changes on network devices are described herein. A user submits intent configuration to the network controller that needs to be delivered to several network sites. The network controller generates a config file. The network controller sends a pull notification message to all network devices that need to retrieve the config file. This pull notification message only contains a corresponding transaction ID for each network device and a location for the network device to use to pull the config file. The network devices may utilize a HTTP REST API exposed by the network controller to obtain the config file from the network controller. The network devices may utilize a REST API exposed by the network controller to reply with statuses of the configuration transaction. The techniques and architecture may be applied to multi-tenant network devices.
    Type: Application
    Filed: March 17, 2023
    Publication date: February 29, 2024
    Inventors: Bhairav Dutia, Manish Jiwansingh Mehra, Upendar Surabhi, Sharmishtha Upadhyay, Sanjeev Pandurang Tondale, Yanbo Zhang, Yogesh Mittal, Nithin Bangalore Raju, Srilatha Tangirala, Balaji Sundararajan
  • Patent number: 7260767
    Abstract: Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8×8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the CRC remainder is compared to a single bit error syndrome table and if an error is located, it is corrected. In the second stage, the CRC remainder is compared to a double bit error syndrome table and if an error is located, it is corrected. The third stage corrects the second error of a double bit error. The flag byte is processed first, followed by the data bytes, eight bytes at a time.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: August 21, 2007
    Assignee: Transwitch Corporation
    Inventors: Santanu Bhattacharya, Neeraj Gupta, Yogesh Mittal, Priya Darshini, Arunava Dutta, Suvhasis Mukhopadhyay
  • Publication number: 20060041826
    Abstract: Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8×8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the CRC remainder is compared to a single bit error syndrome table and if an error is located, it is corrected. In the second stage, the CRC remainder is compared to a double bit error syndrome table and if an error is located, it is corrected. The third stage corrects the second error of a double bit error. The flag byte is processed first, followed by the data bytes, eight bytes at a time.
    Type: Application
    Filed: August 23, 2004
    Publication date: February 23, 2006
    Inventors: Santanu Bhattacharya, Neeraj Gupta, Yogesh Mittal, Priya Darshini, Arunava Dutta, Suvhasis Mukhopadhyay