Abstract: In one example, a method being performed by a computer system comprises: receiving an image file containing a pathology report; performing an image recognition operation on the image file to extract input text strings; detecting, using a natural language processing (NLP) model, entities from the input text strings, each entity including a label and a value; extracting, using the NLP model, the values of the entities from the input text strings; converting, based on a mapping table that maps entities and values to pre-determined terminologies, the values of at least some of the entities to the corresponding pre-determined terminologies; and generating a post-processed pathology report including the entities detected from the input text strings and the corresponding pre-determined terminologies.

Abstract: Methods for depositing metal films using a metal halide and metal organic precursors are described. The substrate is exposed to a first metal precursor and a second metal precursor to form the metal film. The exposures can be sequential or simultaneous. The metal films are relatively pure with a low carbon content.

Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

Abstract: The techniques disclosed herein provision inter-DC WAN capacity based on network failure statistics and bandwidth demands of a cloud-hosted application. Network capacity is provisioned based on an assumption of runtime cooperation between the application and the network. For example, if the network detects that a link has failed, the application may cooperate with the network to pause a deferrable transfer, reserving bandwidth for non-deferrable transfers. With knowledge that deferrable transfers will be dynamically paused when a primary link fails, backup links may be provisioned with less capacity than the primary link. The ability to dynamically defer transfers also enables a greater degree of bandwidth smoothing, e.g. reducing peak demand by scheduling deferrable transfers for off-peak hours. This allows network links to be provisioned with less capacity than if all transfers were performed immediately.

Abstract: The described technology is generally directed towards citizens' broadband radio service (CBRS) channel selection for cellular communication networks in a manner that reduces the risk of CBRS channel revocation due to incumbent activity within a dynamic protection area. A data store can be maintained that includes dynamic protection area location information as well as historic incumbent CBRS channel use information. When selecting a CBRS channel for a radio access network (RAN) node, the position of the RAN node can be considered to determine if the RAN node is in or near a dynamic protection area. If so, the data store can be consulted to avoid selecting CBRS channels that have historically been subject to revocation in the dynamic protection area.

Abstract: The described technology is generally directed towards policy-based citizens broadband radio service (CBRS) channel selection in a cellular communication network. A selection policy can be applied to select CBRS channels for radio access network (RAN) nodes. The selection policy can include performance indicator thresholds, and a CBRS channel can be selected for use at a RAN node when performance indicator measurement values for the CBRS channel satisfy the performance indicator thresholds. The selection policy can be dynamic by applying different performance indicator thresholds under different circumstances such as different traffic conditions experienced at the RAN node.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

Abstract: Embodiments of the disclosure are directed to methods of depositing a molybdenum film directly on a substrate surface (e.g., a low-? dielectric material) by exposing the substrate surface to a molybdenum-containing precursor and an organosilane reducing agent at a temperature of less than or equal to 450° C. The molybdenum-containing precursor comprises one or more of molybdenum pentachloride (MoCl5), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), molybdenum hexafluoride (MoF6), molybdenum hexacarbonyl, bis(tert-butylimido)-bis(dimethylamido)molybdenum, or bis(ethylbenzene) molybdenum. The organosilane reducing agent comprises trimethylsilyl compounds, such as 1,4-bis(trimethylsilyl)-2-methyl-2,5-cyclohexadiene.

Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

Abstract: Embodiments of the disclosure are directed to methods of depositing a molybdenum film directly on a substrate surface (e.g., a low-K dielectric material) by exposing the substrate surface to a molybdenum-containing precursor and a plasma at a temperature of less than or equal to 400° C. The molybdenum-containing precursor comprises one or more of molybdenum pentachloride (MoCl5), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), molybdenum hexacarbonyl, bis(tert-butylimido)-bis(dimethylamido)molybdenum, or bis(ethylbenzene) molybdenum. The plasma comprises one or more of hydrogen (H2), nitrogen (N2), or a silane (SixHy). In some embodiments, when the molybdenum-containing precursor comprises molybdenum hexafluoride (MoF6), the plasma does not include hydrogen (H2).

Abstract: Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include forming a nucleation layer directly on a dielectric layer on a substrate surface by exposing the substrate surface to a molybdenum-containing precursor and a nucleation reactant, and conformally depositing a molybdenum film on the nucleation layer. Another aspect of the disclosure pertains to a method that is part of a gap fill process, comprising forming a nucleation layer directly on a dielectric region within one or more high aspect ratio gap features, including vertical gap features and/or horizontal gap features, and conformally depositing a molybdenum film on the nucleation layer to fill the feature.

Abstract: Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include converting an amorphous silicon layer to a metal layer by thermally soaking the amorphous silicon layer comprising silicon atoms in the presence of a metal compound selected from the group consisting of a molybdenum compound and a tungsten compound until at least a portion of the silicon atoms in the amorphous silicon layer are replaced by metal atoms selected from the group consisting of molybdenum atoms and tungsten atoms. The methods include conformally depositing a molybdenum film on the metal layer.

Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Abstract: Embodiments of the disclosure relate to methods for bottom-up metal gapfill without substantial deposition outside of the feature. Additional embodiments provide a method of forming a metal material on the top surface of the substrate and the bottom of the feature before depositing the metal gapfill.

Abstract: Embodiments of the disclosure advantageously provide in situ selectively deposited molybdenum films having reduced resistivity and methods of reducing or eliminating lateral growth of a selectively deposited molybdenum layer. Additional embodiments provide integrated clean and deposition processes which improve the selectivity of in situ selectively deposited molybdenum films on features, such as a via. Further embodiments advantageously provide methods of improving uniformity and selectivity of bottom-up gap fill for vias with improved film properties.

Abstract: Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III): wherein R1, R2, R3, R4, R5, R6, R7, R8, Ra, Rb, Rc, Rd, Re, and Rf are independently selected from hydrogen (H), substituted alkyl or unsubstituted alkyl; and X, Y, X?, and Y? are independently selected from nitrogen (N) and carbon (C).

Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.