Patents by Inventor Yogesh Vikram Marathe

Yogesh Vikram Marathe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for boot time optimization of embedded multiprocessor systems
    Patent number: 11681534
    Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: June 20, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Yogesh Vikram Marathe, Kedar Satish Chitnis, Rishabh Garg
  • Configuration profiles for graphics processing unit
    Patent number: 11514551
    Abstract: A system may include a graphics processing unit including a command counter. The system may also include a general-purpose processor to: in response to a detection of a timing signal, determine a count value of the command counter included in the graphics processing unit; determine a first threshold range of a plurality of threshold ranges that matches the determined count value of the command counter; select, based on the determined first threshold range, a first configuration profile of a plurality of configuration profiles for the graphics processing unit; and cause the graphics processing unit to use the selected first configuration profile. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Yogesh Vikram Marathe, Ankitkumar Pravinbhai Navik, Praveen Diwakar, Tvrtko Ursulin, Sridhar Muthrasanallur, Aravindan Muthukumar, Kedar J. Karanje, Sujith Thomas, Vipin Anand
  • CONFIGURATION PROFILES FOR GRAPHICS PROCESSING UNIT
    Publication number: 20220101478
    Abstract: A system may include a graphics processing unit including a command counter. The system may also include a general-purpose processor to: in response to a detection of a timing signal, determine a count value of the command counter included in the graphics processing unit; determine a first threshold range of a plurality of threshold ranges that matches the determined count value of the command counter; select, based on the determined first threshold range, a first configuration profile of a plurality of configuration profiles for the graphics processing unit; and cause the graphics processing unit to use the selected first configuration profile. Other embodiments are described and claimed.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: YOGESH VIKRAM MARATHE, Ankitkumar Pravinbhai NAVIK, PRAVEEN DIWAKAR, TVRTKO URSULIN, SRIDHAR MUTHRASANALLUR, ARAVINDAN MUTHUKUMAR, KEDAR J. KARANJE, SUJITH THOMAS, VIPIN ANAND
  • METHOD AND SYSTEM FOR BOOT TIME OPTIMIZATION OF EMBEDDED MULTIPROCESSOR SYSTEMS
    Publication number: 20210232406
    Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.
    Type: Application
    Filed: March 23, 2021
    Publication date: July 29, 2021
    Inventors: Yogesh Vikram Marathe, Kedar Satish Chitnis, Rishabh Garg
  • Method and system for boot time optimization of embedded multiprocessor systems
    Patent number: 10956169
    Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Yogesh Vikram Marathe, Kedar Satish Chitnis, Rishabh Garg
  • Method and System for Boot Time Optimization of Embedded Multiprocessor Systems
    Publication number: 20170123810
    Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.
    Type: Application
    Filed: March 31, 2016
    Publication date: May 4, 2017
    Inventors: Yogesh Vikram Marathe, Kedar Satish Chitnis, Rishabh Garg