Patents by Inventor Yoh Matsuda

Yoh Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11715704
    Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hidenori Yamaguchi, Yoh Matsuda, Yuta Nomura
  • Publication number: 20220336373
    Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.
    Type: Application
    Filed: April 14, 2021
    Publication date: October 20, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Hidenori Yamaguchi, Yoh Matsuda, Yuta Nomura
  • Patent number: 8603892
    Abstract: A semiconductor device includes groove-like regions that are formed between two adjacent bit lines among a plurality of bit lines each having upper and side surfaces covered with a cap insulating film and a side-wall insulating film, respectively, a SiON film that contains more O (oxygen) than N (nitrogen) and continuously covers inner surfaces of the groove-like regions, and a silicon dioxide film formed by reforming polysilazane and filled in the groove-like regions with the SiON film interposed therebetween.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: December 10, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Yoh Matsuda, Kyoko Miyata
  • Publication number: 20120164816
    Abstract: A semiconductor device includes groove-like regions that are formed between two adjacent bit lines among a plurality of bit lines each having upper and side surfaces covered with a cap insulating film and a side-wall insulating film, respectively, a SiON film that contains more O (oxygen) than N (nitrogen) and continuously covers inner surfaces of the groove-like regions, and a silicon dioxide film formed by reforming polysilazane and filled in the groove-like regions with the SiON film interposed therebetween.
    Type: Application
    Filed: March 7, 2012
    Publication date: June 28, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yoh MATSUDA, Kyoko MIYATA
  • Patent number: 8154102
    Abstract: A semiconductor device includes groove-like regions that are formed between two adjacent bit lines among a plurality of bit lines each having upper and side surfaces covered with a cap insulating film and a side-wall insulating film, respectively, a SiON film that contains more O (oxygen) than N (nitrogen) and continuously covers inner surfaces of the groove-like regions, and a silicon dioxide film formed by reforming polysilazane and filled in the groove-like regions with the SiON film interposed therebetween.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: April 10, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yoh Matsuda, Kyoko Miyata
  • Publication number: 20100148301
    Abstract: A semiconductor device includes groove-like regions that are formed between two adjacent bit lines among a plurality of bit lines each having upper and side surfaces covered with a cap insulating film and a side-wall insulating film, respectively, a SiON film that contains more O (oxygen) than N (nitrogen) and continuously covers inner surfaces of the groove-like regions, and a silicon dioxide film formed by reforming polysilazane and filled in the groove-like regions with the SiON film interposed therebetween.
    Type: Application
    Filed: December 16, 2009
    Publication date: June 17, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yoh MATSUDA, Kyoko MIYATA