Abstract: Apparatuses and methods relating to controlling cache evictions are disclosed. Processing circuitry which execute instructions out-of-order is provided with a private cache into which blocks of data are copied from a shared storage location to which the processing circuitry shares access. The processing circuitry also has a read-after-read buffer, into which an entry is allocated when out-of-order execution of a load instruction occurs comprising an address accessed by the load instruction. The address remains as a valid entry in the read-after-read buffer until the load instruction is committed. Eviction of an eviction candidate block of data from the private cache to the shared storage location is controlled in dependence on whether the eviction candidate block of data has a corresponding valid entry in the read-after-read buffer.