Patents by Inventor Yohan Frans

Yohan Frans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250087252
    Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.
    Type: Application
    Filed: October 17, 2024
    Publication date: March 13, 2025
    Inventor: Yohan Frans
  • Publication number: 20240405882
    Abstract: Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a data pattern to an optical modulator device. The method also includes identifying, for each heater control value of a plurality of heater control values for a heater thermally coupled with the optical modulator device, an optical modulation amplitude corresponding to the heater control value based on a corresponding photodiode current value identified while transmitting the data pattern. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based on a plurality of optical modulation amplitudes corresponding to the plurality of heater control values according to the identifying. The method also includes controlling the heater based at least in part on the determined maximum optical modulation amplitude that has been modified according to scaling maximum photodiode current values.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 5, 2024
    Inventors: Adebabay M. BEKELE, Mayank RAJ, Chuan XIE, Sandeep KUMAR, Zhaowen WANG, Sukruth PATTANAGIRI GIRIYAPPA, Parag UPADHYAYA, Yohan FRANS
  • Publication number: 20240396638
    Abstract: Some examples described herein provide for controlling output modulation amplitude for optoelectronic devices. In an example, a method includes transmitting a first data pattern to an optical modulator device. The method also includes determining, while transmitting the first data pattern and for each heater control value of a plurality of heater control values for a heater, a photodiode current value associated with the optical modulator device to generate a plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes determining a maximum optical modulation amplitude for the optical modulator device based at least in part on the plurality of photodiode current values corresponding to the plurality of heater control values. The method also includes controlling the heater for the optical modulator device based on the maximum optical modulation amplitude.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 28, 2024
    Inventors: Adebabay M. BEKELE, Mayank RAJ, Chuan XIE, Sandeep KUMAR, Zhaowen WANG, Sukruth PATTANAGIRI GIRIYAPPA, Parag UPADHYAYA, Yohan FRANS
  • Publication number: 20240369864
    Abstract: A silicon-on-insulator (SOI) dense-wavelength-division-multiplexing (DWDM) device includes micro-ring modulators (MRMs) having radii under 5 micrometers. A 16-channel embodiment may provide a free spectral range of 3.2 THz, 200 GHz channel spacing, 41 GHz bandwidth, and a Q factor of 4500. PN junctions of rib ring waveguides (RWRs) may be perpendicular or parallel with a plane of the RWRs. On-chip inductive components may be used to match reactances of the PN junctions. The RWRs may be relatively wide and a rib bus waveguide may be relatively narrow (e.g., narrower than the RWRs). MRM outer slaps may be wider than inner slabs. Regions inside and outside of the RWRs, including slabs at optical coupling gaps may be doped to improve modulation efficiency. Regions of the rib bus waveguide distant from the optical coupling gaps may be undoped. Cavities may be provided below the MRMs and associated heater elements.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 7, 2024
    Applicant: XILINX, INC.
    Inventors: Chuan XIE, Mayank RAJ, Anish JOSHI, Zakriya MOHAMMED, Gareeyasee SAHA, Parag UPADHYAYA, Yohan FRANS
  • Patent number: 12131796
    Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: October 29, 2024
    Assignee: Rambus Inc.
    Inventor: Yohan Frans
  • Publication number: 20240313135
    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.
    Type: Application
    Filed: April 1, 2024
    Publication date: September 19, 2024
    Inventors: Yohan Frans, Simon Li, John Eric Linstadt, Jun Kim
  • Patent number: 12072239
    Abstract: An integrated circuit (IC) device includes a controller circuitry having an input coupled to a photodiode of an optoelectronic circuitry and an output coupled to a heater of the optoelectronic circuitry, the controller circuitry configured to determine a center frequency of the optoelectronic circuitry based on a shape of an input signal received from the photodiode, and provide a heater signal to the heater based on the shape of the input signal and the center frequency of the optoelectronic circuitry.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: August 27, 2024
    Assignee: XILINX, INC.
    Inventors: Zhaowen Wang, Mayank Raj, Chuan Xie, Sandeep Kumar, Muqseed Mohammad, Sukruth Pattanagiri Giriyappa, Stanley Y. Chen, Parag Upadhyaya, Yohan Frans
  • Patent number: 12063129
    Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: August 13, 2024
    Assignee: XILINX, INC.
    Inventors: Hongtao Zhang, Winson Lin, Arianne Roldan, Yohan Frans, Geoff Zhang
  • Patent number: 11973153
    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: April 30, 2024
    Assignee: Rambus Inc.
    Inventors: Yohan Frans, Simon Li, John Eric Linstadt, Jun Kim
  • Publication number: 20230395103
    Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.
    Type: Application
    Filed: May 10, 2023
    Publication date: December 7, 2023
    Inventor: Yohan Frans
  • Patent number: 11769710
    Abstract: Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: September 26, 2023
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Ken Chang, Mayank Raj, Chuan Xie, Yohan Frans
  • Publication number: 20230282547
    Abstract: Chip packages and methods for fabricating the same are provided which utilize a first heat spreader interfaced with a first integrated circuit (IC) die and a second heat spreader separately interfaced with a second IC die. The separate heat spreaders allow the force applied to the first IC die to be controlled independent of the force applied to the second IC die.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 7, 2023
    Inventors: Gamal REFAI-AHMED, Yohan FRANS, Suresh RAMALINGAM
  • Patent number: 11651801
    Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: May 16, 2023
    Assignee: Rambus Inc.
    Inventor: Yohan Frans
  • Publication number: 20220231889
    Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.
    Type: Application
    Filed: February 4, 2022
    Publication date: July 21, 2022
    Inventors: Hongtao ZHANG, Winson LIN, Arianne ROLDAN, Yohan FRANS, Geoff ZHANG
  • Publication number: 20220077327
    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.
    Type: Application
    Filed: August 18, 2021
    Publication date: March 10, 2022
    Inventors: Yohan Frans, Simon Li, John Eric Linstadt, Jun Kim
  • Patent number: 11245554
    Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: February 8, 2022
    Assignee: XILINX, INC.
    Inventors: Hongtao Zhang, Winson Lin, Arianne Roldan, Yohan Frans, Geoff Zhang
  • Publication number: 20210305127
    Abstract: Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Inventors: Gamal REFAI-AHMED, Suresh RAMALINGAM, Ken CHANG, Mayank RAJ, Chuan XIE, Yohan FRANS
  • Patent number: 11107770
    Abstract: An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided between the electrical/optical interface die and the optical dies, and a third routing region is disposed between the substrate and the core and electrical/optical interface dies.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 31, 2021
    Assignee: XILINX, INC.
    Inventors: Suresh Ramalingam, Kun-Yung Chang, Yohan Frans, Chuan Xie, Mayank Raj
  • Patent number: 11101393
    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 24, 2021
    Assignee: Rambus Inc.
    Inventors: Yohan Frans, Simon Li, John Eric Linstadt, Jun Kim
  • Publication number: 20210217448
    Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.
    Type: Application
    Filed: December 28, 2020
    Publication date: July 15, 2021
    Inventor: Yohan Frans