Patents by Inventor Yohan Frans
Yohan Frans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240369864Abstract: A silicon-on-insulator (SOI) dense-wavelength-division-multiplexing (DWDM) device includes micro-ring modulators (MRMs) having radii under 5 micrometers. A 16-channel embodiment may provide a free spectral range of 3.2 THz, 200 GHz channel spacing, 41 GHz bandwidth, and a Q factor of 4500. PN junctions of rib ring waveguides (RWRs) may be perpendicular or parallel with a plane of the RWRs. On-chip inductive components may be used to match reactances of the PN junctions. The RWRs may be relatively wide and a rib bus waveguide may be relatively narrow (e.g., narrower than the RWRs). MRM outer slaps may be wider than inner slabs. Regions inside and outside of the RWRs, including slabs at optical coupling gaps may be doped to improve modulation efficiency. Regions of the rib bus waveguide distant from the optical coupling gaps may be undoped. Cavities may be provided below the MRMs and associated heater elements.Type: ApplicationFiled: May 5, 2023Publication date: November 7, 2024Applicant: XILINX, INC.Inventors: Chuan XIE, Mayank RAJ, Anish JOSHI, Zakriya MOHAMMED, Gareeyasee SAHA, Parag UPADHYAYA, Yohan FRANS
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Patent number: 12131796Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.Type: GrantFiled: May 10, 2023Date of Patent: October 29, 2024Assignee: Rambus Inc.Inventor: Yohan Frans
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Publication number: 20240313135Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.Type: ApplicationFiled: April 1, 2024Publication date: September 19, 2024Inventors: Yohan Frans, Simon Li, John Eric Linstadt, Jun Kim
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Patent number: 12072239Abstract: An integrated circuit (IC) device includes a controller circuitry having an input coupled to a photodiode of an optoelectronic circuitry and an output coupled to a heater of the optoelectronic circuitry, the controller circuitry configured to determine a center frequency of the optoelectronic circuitry based on a shape of an input signal received from the photodiode, and provide a heater signal to the heater based on the shape of the input signal and the center frequency of the optoelectronic circuitry.Type: GrantFiled: March 30, 2023Date of Patent: August 27, 2024Assignee: XILINX, INC.Inventors: Zhaowen Wang, Mayank Raj, Chuan Xie, Sandeep Kumar, Muqseed Mohammad, Sukruth Pattanagiri Giriyappa, Stanley Y. Chen, Parag Upadhyaya, Yohan Frans
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Patent number: 12063129Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.Type: GrantFiled: February 4, 2022Date of Patent: August 13, 2024Assignee: XILINX, INC.Inventors: Hongtao Zhang, Winson Lin, Arianne Roldan, Yohan Frans, Geoff Zhang
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Patent number: 11973153Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.Type: GrantFiled: August 18, 2021Date of Patent: April 30, 2024Assignee: Rambus Inc.Inventors: Yohan Frans, Simon Li, John Eric Linstadt, Jun Kim
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Publication number: 20230395103Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.Type: ApplicationFiled: May 10, 2023Publication date: December 7, 2023Inventor: Yohan Frans
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Patent number: 11769710Abstract: Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.Type: GrantFiled: March 27, 2020Date of Patent: September 26, 2023Assignee: XILINX, INC.Inventors: Gamal Refai-Ahmed, Suresh Ramalingam, Ken Chang, Mayank Raj, Chuan Xie, Yohan Frans
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Publication number: 20230282547Abstract: Chip packages and methods for fabricating the same are provided which utilize a first heat spreader interfaced with a first integrated circuit (IC) die and a second heat spreader separately interfaced with a second IC die. The separate heat spreaders allow the force applied to the first IC die to be controlled independent of the force applied to the second IC die.Type: ApplicationFiled: March 7, 2022Publication date: September 7, 2023Inventors: Gamal REFAI-AHMED, Yohan FRANS, Suresh RAMALINGAM
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Patent number: 11651801Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.Type: GrantFiled: December 28, 2020Date of Patent: May 16, 2023Assignee: Rambus Inc.Inventor: Yohan Frans
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Publication number: 20220231889Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.Type: ApplicationFiled: February 4, 2022Publication date: July 21, 2022Inventors: Hongtao ZHANG, Winson LIN, Arianne ROLDAN, Yohan FRANS, Geoff ZHANG
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Publication number: 20220077327Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.Type: ApplicationFiled: August 18, 2021Publication date: March 10, 2022Inventors: Yohan Frans, Simon Li, John Eric Linstadt, Jun Kim
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Patent number: 11245554Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.Type: GrantFiled: June 17, 2020Date of Patent: February 8, 2022Assignee: XILINX, INC.Inventors: Hongtao Zhang, Winson Lin, Arianne Roldan, Yohan Frans, Geoff Zhang
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Publication number: 20210305127Abstract: Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Inventors: Gamal REFAI-AHMED, Suresh RAMALINGAM, Ken CHANG, Mayank RAJ, Chuan XIE, Yohan FRANS
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Patent number: 11107770Abstract: An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided between the electrical/optical interface die and the optical dies, and a third routing region is disposed between the substrate and the core and electrical/optical interface dies.Type: GrantFiled: June 27, 2019Date of Patent: August 31, 2021Assignee: XILINX, INC.Inventors: Suresh Ramalingam, Kun-Yung Chang, Yohan Frans, Chuan Xie, Mayank Raj
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Patent number: 11101393Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.Type: GrantFiled: November 4, 2019Date of Patent: August 24, 2021Assignee: Rambus Inc.Inventors: Yohan Frans, Simon Li, John Eric Linstadt, Jun Kim
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Publication number: 20210217448Abstract: A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.Type: ApplicationFiled: December 28, 2020Publication date: July 15, 2021Inventor: Yohan Frans
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Patent number: 11043470Abstract: Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.Type: GrantFiled: November 25, 2019Date of Patent: June 22, 2021Assignee: XILINX, INC.Inventors: Jing Jing, Shuxian Wu, Xin X. Wu, Yohan Frans
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Patent number: 11038768Abstract: A method relates generally to comparison of a communications system modelled with a behavioral model and implemented with a circuit realization. In this method, operation of the communications system is simulated with the behavioral model on a computing device to obtain a first pulse response. The simulating includes first equalizing first data with a first equalizer of the behavioral model to obtain the first pulse response. The circuit realization is operated to obtain a second pulse response. The operating includes: second equalizing second data corresponding to the first data with a second equalizer of the circuit realization to obtain the second pulse response. The second pulse response from the circuit realization is loaded to memory of the computing device. The first pulse is loaded to the memory of the computing device. The first pulse response and the second pulse response are compared with one another by the computing device.Type: GrantFiled: September 15, 2016Date of Patent: June 15, 2021Assignee: XILINX, INC.Inventors: Ivan O. Madrigal, Michael O. Jenkins, Hong S. Ahn, Murtuza Z. Cutleriwala, Alan C. Wong, Christopher J. Borrelli, Yohan Frans, Geoffrey Zhang, Hongtao Zhang
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Publication number: 20210159212Abstract: Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.Type: ApplicationFiled: November 25, 2019Publication date: May 27, 2021Inventors: Jing JING, Shuxian WU, Xin X. WU, Yohan FRANS