Abstract: A semiconductor circuit configured to reduce electromigration. The circuit comprises a power rail and ground rail located on a first layer. A power finger and a ground finger are located on a second layer. Cells are located on the second layer, such that the one or more cells are electrically connected to a power finger and a ground finger. The circuit also includes one or more power vias electrically connecting the power rail to the power finger. The one or more power vias extend from the first layer to the second layer. One or more ground vias electrically connecting the ground rail to the ground finger, such that the one or more ground vias extend from the first layer to the second layer. The placement of the fingers on a different level than the rails establishing the fingers as non-contiguous sections thereby reducing electromigration and overcoming design analysis errors.

Abstract: A semiconductor circuit configured to reduce electromigration. The circuit comprises a power rail and ground rail located on a first layer. A power finger and a ground finger are located on a second layer. Cells are located on the second layer, such that the one or more cells are electrically connected to a power finger and a ground finger. The circuit also includes one or more power vias electrically connecting the power rail to the power finger. The one or more power vias extend from the first layer to the second layer. One or more ground vias electrically connecting the ground rail to the ground finger, such that the one or more ground vias extend from the first layer to the second layer. The placement of the fingers on a different level than the rails establishing the fingers as non-contiguous sections thereby reducing electromigration and overcoming design analysis errors.