Patents by Inventor Yohan U. Frans
Yohan U. Frans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11886375Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.Type: GrantFiled: May 23, 2022Date of Patent: January 30, 2024Assignee: RAMBUS INC.Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen
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Publication number: 20230051578Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.Type: ApplicationFiled: May 23, 2022Publication date: February 16, 2023Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen
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Publication number: 20220223224Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: ApplicationFiled: December 20, 2021Publication date: July 14, 2022Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
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Patent number: 11341079Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.Type: GrantFiled: October 21, 2019Date of Patent: May 24, 2022Assignee: RAMBUS INC.Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen
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Patent number: 11211139Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: GrantFiled: March 19, 2020Date of Patent: December 28, 2021Assignee: Rambus Inc.Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
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Publication number: 20200312422Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: ApplicationFiled: March 19, 2020Publication date: October 1, 2020Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
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Publication number: 20200159688Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.Type: ApplicationFiled: October 21, 2019Publication date: May 21, 2020Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen
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Patent number: 10600497Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: GrantFiled: December 19, 2017Date of Patent: March 24, 2020Assignee: Rambus Inc.Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
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Patent number: 10452601Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.Type: GrantFiled: April 6, 2018Date of Patent: October 22, 2019Assignee: RAMBUS INC.Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen
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Publication number: 20180329859Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.Type: ApplicationFiled: April 6, 2018Publication date: November 15, 2018Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen
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Publication number: 20180174667Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: ApplicationFiled: December 19, 2017Publication date: June 21, 2018Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
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Patent number: 9940299Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.Type: GrantFiled: December 28, 2016Date of Patent: April 10, 2018Assignee: RAMBUS INC.Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen
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Patent number: 9859021Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: GrantFiled: October 15, 2015Date of Patent: January 2, 2018Assignee: Rambus Inc.Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
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Publication number: 20170177540Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.Type: ApplicationFiled: December 28, 2016Publication date: June 22, 2017Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen
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Patent number: 9569396Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.Type: GrantFiled: November 3, 2015Date of Patent: February 14, 2017Assignee: Rambus Inc.Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen
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Patent number: 9431131Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.Type: GrantFiled: January 20, 2015Date of Patent: August 30, 2016Assignee: Rambus Inc.Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
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Patent number: 9401225Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.Type: GrantFiled: November 10, 2011Date of Patent: July 26, 2016Assignee: Rambus Inc.Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
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Patent number: 9362006Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.Type: GrantFiled: December 15, 2014Date of Patent: June 7, 2016Assignee: Rambus Inc.Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
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Patent number: 9349422Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., ½, ¼ or ? of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.Type: GrantFiled: April 15, 2015Date of Patent: May 24, 2016Assignee: Rambus Inc.Inventors: Akash Bansal, Yohan U. Frans, Kishore V. Kasamsetty, Todd Bystrom, Simon Li, Arun Vaidyanath
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Publication number: 20160124895Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.Type: ApplicationFiled: November 3, 2015Publication date: May 5, 2016Inventors: Yohan U. Frans, Hae-Chang Lee, Brian S. Leibowitz, Simon Li, Nhat M. Nguyen