Patents by Inventor Yohan Usthavia Frans

Yohan Usthavia Frans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9836428
    Abstract: A memory controller and/or memory device control termination of a communication link in order to achieve power savings while reducing or eliminating unwanted reflections in the channel. Following transmission of data over the communication channel, termination is left enabled for a programmable time period beginning immediately following completion of the transmission. The time period is sufficiently long to allow the unwanted reflections to be absorbed by the termination. Following the time period, the termination is disabled for power savings.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: December 5, 2017
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Pravin Kumar Venkatesan, Yohan Usthavia Frans
  • Patent number: 9330034
    Abstract: In a memory system in which a system clock signal is forwarded from the memory controller to multiple memory devices, the phase of the system clock signal forwarded to the slower memory device is advanced relative to the system clock signal forwarded to the faster memory device by a phase corresponding to the skew on the data links corresponding to the memory devices. This causes the state machine of the slower memory device to change states and advance earlier than the state machine in the faster memory device, and as a result, the data read from both the slower memory device and the faster memory device are unskewed on the data links between the memory controller and the memory devices.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: May 3, 2016
    Assignee: Rambus Inc.
    Inventors: Yohan Usthavia Frans, Simon Li
  • Patent number: 9129666
    Abstract: A memory device is placed in a mode that redefines the command set used to control the memory device. This may occur either in anticipation of the memory system falling out of calibration, or after it has already fallen out of calibration. The redefined command set is designed such that it may be reliably received by the memory device at the specified rate even if the memory system has fallen out of calibration. The redefined command set is then used to issue command(s) to recalibrate one or more communication links such that they can exchange data, commands, and/or addresses at a specified rate. After recalibration, the memory device is returned to responding to the original command set.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: September 8, 2015
    Assignee: Rambus Inc.
    Inventors: Wayne S. Richardson, Wayne Frederick Ellis, Yohan Usthavia Frans, Lawrence Lai
  • Publication number: 20150205751
    Abstract: A memory controller and/or memory device control termination of a communication link in order to achieve power savings while reducing or eliminating unwanted reflections in the channel. Following transmission of data over the communication channel, termination is left enabled for a programmable time period beginning immediately following completion of the transmission. The time period is sufficiently long to allow the unwanted reflections to be absorbed by the termination. Following the time period, the termination is disabled for power savings.
    Type: Application
    Filed: July 17, 2013
    Publication date: July 23, 2015
    Inventors: Kyung Suk Oh, Pravin Kumar Venkatesan, Yohan Usthavia Frans
  • Publication number: 20130013878
    Abstract: In a memory system in which a system clock signal is forwarded from the memory controller to multiple memory devices, the phase of the system clock signal forwarded to the slower memory device is advanced relative to the system clock signal forwarded to the faster memory device by a phase corresponding to the skew on the data links corresponding to the memory devices. This causes the state machine of the slower memory device to change states and advance earlier than the state machine in the faster memory device, and as a result, the data read from both the slower memory device and the faster memory device are unskewed on the data links between the memory controller and the memory devices.
    Type: Application
    Filed: March 30, 2011
    Publication date: January 10, 2013
    Applicant: RAMBUS INC.
    Inventors: Yohan Usthavia Frans, Simon Li