Abstract: Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

Abstract: Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

Abstract: Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

Abstract: Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

Abstract: Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

Abstract: Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.