Patents by Inventor Yohei Enya

Yohei Enya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100260224
    Abstract: A primary surface 23a of a supporting base 23 of a light-emitting diode 21a tilts by an off-angle of 10 degrees or more and less than 80 degrees from the c-plane. A semiconductor stack 25a includes an active layer having an emission peak in a wavelength range from 400 nm to 550 nm. The tilt angle “A” between the (0001) plane (the reference plane SR3 shown in FIG. 5) of the GaN supporting base and the (0001) plane of a buffer layer 33a is 0.05 degree or more and 2 degrees or less. The tilt angle “B” between the (0001) plane of the GaN supporting base (the reference plane SR4 shown in FIG. 5) and the (0001) plane of a well layer 37a is 0.05 degree or more and 2 degrees or less. The tilt angles “A” and “B” are formed in respective directions opposite to each other with reference to the c-plane of the GaN supporting base.
    Type: Application
    Filed: May 13, 2010
    Publication date: October 14, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yusuke YOSHIZUMI, Yohei ENYA, Masaki UENO, Fumitake NAKANISHI
  • Publication number: 20100230690
    Abstract: A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device 11a includes a group III nitride semiconductor supporting base 13, a GaN based semiconductor region 15, an active layer active layer 17, and a GaN semiconductor region 19. The primary surface 13a of the group III nitride semiconductor supporting base 13 is not any polar plane, and forms a finite angle with a reference plane Sc that is orthogonal to a reference axis Cx extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region 15 is grown on the semipolar primary surface 13a. A GaN based semiconductor layer 21 of the GaN based semiconductor region 15 is, for example, an n-type GaN based semiconductor, and the n-type GaN based semiconductor is doped with silicon.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 16, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi KYONO, Yusuke YOSHIZUMI, Yohei ENYA, Katsushi AKITA, Masaki UENO, Takamichi SUMITOMO, Takao NAKAMURA
  • Publication number: 20100220761
    Abstract: A gallium nitride-based semiconductor optical device is provided that includes an indium-containing gallium nitride-based semiconductor layer that exhibit low piezoelectric effect and high crystal quality. The gallium nitride-based semiconductor optical device 11a includes a GaN support base 13, a GaN-based semiconductor region 15, and well layers 19. A primary surface 13a tilts from a surface orthogonal to a reference axis that extends in a direction from one crystal axis of the m-axis and the a-axis of GaN toward the other crystal axis. The tilt angle AOFF is equal to the angle defined by a vector VM and a vector VN. The inclination of the primary surface is shown by a typical m-plane SM and m-axis vector VM. The GaN-based semiconductor region 15 is provided on the primary surface 13a. In the well layers 19 in an active layer 17, both the m-plane and the a-plane of the well layers 19 tilt from a normal axis AN of the primary surface 13a. The indium content of the well layers 19 is 0.1 or more.
    Type: Application
    Filed: March 2, 2010
    Publication date: September 2, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yohei ENYA, Yusuke YOSHIZUMI, Hideki OSADA, Keiji ISHIBASHI, Katsushi AKITA, Masaki UENO
  • Publication number: 20100213439
    Abstract: In the nitride based semiconductor optical device LE1, the strained well layers 21 extend along a reference plane SR1 tilting at a tilt angle ? from the plane that is orthogonal to a reference axis extending in the direction of the c-axis. The tilt angle ? is in the range of greater than 59 degrees to less than 80 degrees or greater than 150 degrees to less than 180 degrees. A gallium nitride based semiconductor layer P is adjacent to a light-emitting layer SP? with a negative piezoelectric field and has a band gap larger than that of a barrier layer. The direction of the piezoelectric field in the well layer W3 is directed in a direction from the n-type layer to the p-type layer, and the piezoelectric field in the gallium nitride based semiconductor layer P is directed in a direction from the p-type layer to the n-type layer. Consequently, the valence band, not the conduction band, has a dip at the interface between the light-emitting layer SP? and the gallium nitride based semiconductor layer P.
    Type: Application
    Filed: April 1, 2010
    Publication date: August 26, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Masaki Ueno, Yohei Enya, Takashi Kyono, Katsushi Akita, Yusuke Yoshizumi, Takamichi Sumitomo, Takao Nakamura
  • Publication number: 20100190284
    Abstract: In the method of fabricating a nitride-based semiconductor optical device by metal-organic chemical vapor deposition, a barrier layer is grown at a first temperature while supplying a gallium source to a reactor. The barrier layer comprises a first gallium nitride-based semiconductor. After the growth of the barrier layer, a nitrogen material and an indium material are supplied to the reactor without supply of the gallium source to perform a preflow of indium. Immediately after the preflow, a well layer is grown on the barrier layer at a second temperature while supplying an indium source and the gallium source to the reactor. The well layer comprises InGaN, and the second temperature is lower than the first temperature. The gallium source and the indium source are supplied to the reactor during plural first periods of the step of growing the well layer to grow plural InGaN layers, respectively.
    Type: Application
    Filed: January 22, 2010
    Publication date: July 29, 2010
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yohei ENYA, Yusuke YOSHIZUMI, Masaki UENO, Takashi KYONO, Katsushi AKITA
  • Publication number: 20100055820
    Abstract: In step S106, an InXGa1-XN well layer is grown on a semipolar main surface between times t4 and t5 while a temperature in a growth furnace is maintained at temperature TW. In step S107, immediately after completion of the growth of the well layer, the growth of a protective layer covering the main surface of the well layer is initiated at temperature TW. The protective layer is composed of a gallium nitride-based semiconductor with a band gap energy that is higher than that of the well layer and equal to or less than that of a barrier layer. In step S108, the temperature in the furnace is changed from temperatures TW to TB before the barrier layer growth. The barrier layer composed of the gallium nitride-based semiconductor is grown on the protective layer between times t8 and t9 while the temperature in the furnace is maintained at temperature TB.
    Type: Application
    Filed: August 12, 2009
    Publication date: March 4, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Katsushi Akita, Yohei Enya, Takashi Kyono, Takamichi Sumitomo, Yusuke Yoshizumi, Masaki Ueno, Takao Nakamura
  • Publication number: 20100008393
    Abstract: The group II nitride semiconductor light-emitting device includes: a gallium nitride based semiconductor region of n-type; a p-type gallium nitride based semiconductor region; a hole-blocking layer; and an active layer. The gallium nitride based semiconductor region of n-type has a primary surface, and the primary surface extends on a predetermined plane. The c-axis of the gallium nitride based semiconductor region tilts from a normal line of the predetermined plane. The hole-blocking layer comprises a first gallium nitride based semiconductor. The band gap of the hole-blocking layer is greater than the band gap of the gallium nitride based semiconductor region, and the thickness of the hole-blocking layer is less than the thickness of the gallium nitride based semiconductor region. The active layer comprises a gallium nitride semiconductor. The active layer is provided between the p-type gallium nitride based semiconductor region and the hole-blocking layer.
    Type: Application
    Filed: July 9, 2009
    Publication date: January 14, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yohei Enya, Takashi Kyono, Katsushi Akita, Masaki Ueno
  • Publication number: 20100009484
    Abstract: In the method of fabricating a quantum well structure which includes a well layer and a barrier layer, the well layer is grown at a first temperature on a sapphire substrate. The well layer comprises a group III nitride semiconductor which contains indium as a constituent. An intermediate layer is grown on the InGaN well layer while monotonically increasing the sapphire substrate temperature from the first temperature. The group III nitride semiconductor of the intermediate layer has a band gap energy larger than the band gap energy of the InGaN well layer, and a thickness of the intermediate layer is greater than 1 nm and less than 3 nm in thickness. The barrier layer is grown on the intermediate layer at a second temperature higher than the first temperature. The barrier layer comprising a group III nitride semiconductor and the group III nitride semiconductor of the barrier layer has a band gap energy larger than the band gap energy of the well layer.
    Type: Application
    Filed: July 9, 2009
    Publication date: January 14, 2010
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Katsushi AKITA, Takamichi SUMITOMO, Yohei ENYA, Takashi KYONO, Masaki UENO
  • Publication number: 20090258452
    Abstract: A method for forming a quantum well structure that can reduce the variation in the In composition in the thickness direction of a well layer and a method for manufacturing a semiconductor light emitting element are provided. In a step of forming a quantum well structure (active layer) by alternately growing barrier layers and well layers on a primary surface of a GaN substrate, the well layers are each formed by growing InGaN, the barrier layers are each grown at a first temperature, the well layers are each grown at a second temperature which is lower than that of the first temperature, and when the well layers are each formed, before a starting material gas for Ga (trimethylgallium) is supplied, a starting material gas for In is supplied.
    Type: Application
    Filed: April 3, 2009
    Publication date: October 15, 2009
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yohei ENYA, Yusuke YOSHIZUMI, Masaki UENO, Fumitake NAKANISHI